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preliminary rev. 0.8 2/12 copyright ? 2012 by silicon laboratories sim3c1xx this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. sim3c1xx high-performance, low-power, 32-bit precision32? mcu family with up to 256 kb of flash 32-bit arm? cortex?-m3 cpu - 80 mhz maximum frequency - single-cycle multiplication, hardware division support - nested vectored interrupt control (nvic) with 16 levels of ? interrupt priority memory - 32?256 kb flash, in-system programmable - 8?32 kb sram (including 4 kb retention sram) - external bus interface supports up to 16 mb of external mem - ory and a parallel lcd interface with qvga resolution power management - low drop-out (ldo) regulator - power-on reset circuit and brownout detectors - 5-to-3.3 v voltage regulator supports up to 150 ma to drive the device directly from up to 5 v supply - programmable external regulator supports up to 3.6 v, 1000 ma - multiple power modes supported for low power optimization clock sources - internal oscillator with pll: fine frequency resolution up to 80 mhz; spread-spectrum mode for reduced emi - low power internal oscillator: 20 mhz and 2.5 mhz modes - low frequency internal oscillator: 16.4 khz - external oscillators: crystal, rc, c, cmos and rtc crystal - flexible clock divider: reduce frequency by up to 128x from any clock source 128/192/256-bit hardware aes encryption - hardware-supported electronic codebook (ecb), cipher-block chaining (cbc) and counter (ctr) algorithms - all cipher operations can be perfo rmed without any firmware intervention for a set of 4-word blocks (up to 32 kb) 16/32-bit crc - hardware support for common 32-bit and 16-bit polynomials timers/counters - 2 x 32-bit or 4 x 16-bit timers with capture/compare - 2 x 16-bit, 2-channel counters with capture/compare/pwm - 16-bit, 6-channel counter with capture/compare/pwm and dead-time controller with differential outputs - 16-bit low power timer/pulse counter operational in the lowest power mode - 32-bit real time clock (rtc) with multiple alarms - watchdog timer current-to-voltage converter - supports up to 6 ma input range supply voltage - 2.7 to 5.5 v (regulator enabled) - 1.8 to 3.6 v (regulator disabled) low power features - 85 na current mode with voltage supply monitor enabled - 350 na current mode with rtc (internal oscillator) - 620 na current mode with rtc (external oscillator) - 10 s wakeup (lowest power mode); 1.5 s analog setting time - 275 a/mhz active current - clocks can be gated off from unused peripherals to save power 2 x 12-bit analog-to-digital converters - up to 28 input channels - up to 250 ksps 12-bit mode or 1 msps 10-bit mode - single, simultaneous, and interleaving modes supported - channel sequencer enables automatic multiplexing of multiple channels without firmware intervention - internal vref or external vref supported 2 x 10-bit digital-to-analog converters - dma support for waveform generation - four-word circular buffer to enable 12-bit mode 16-channel capacitance-to-digital converter - supports buttons, sliders, wheels, and capacitive proximity - fast conversion time; <1 a wake-on-touch average current two low-current comparators - integrated 6-bit programmable reference voltage - 400 na current consumption in low power mode 16-channel dma controller - supports adc, dac, i2c, i 2 s, spi, usart, aes, epca, capacitive sensing, external triggers, and timers up to 65 flexible i/o - up to 59 contiguous gpio with tw o priority crossbars providing flexibility in pin assignments; 12 x 5 v tolerant gpio - up to 6 programmable high drive capable (5?300 ma, 1.8?6 v) i/o can drive leds, power mosfets, buzzers, etc. communication interfaces - 2 x usarts and 2 x uarts with irda and iso7816 smartcard - 3 x spis, 2 x i2c, i 2 s (receive and transmit) on-chip debugging - serial wire debug (swd) and jtag allow for full-speed, non- intrusive debug - serial wire viewer (swv) avai lable in 64 / 80 / 92-pin packages - cortex-m3 embedded trace macrocell (etm) in 80 / 92-pin packages temperature range: ?40 to +85 c package options - qfn options: 40-pin (6 x 6 mm), 64-pin (9 x 9 mm) - tqfp options: 64-pin (10 x 10 mm), 80-pin (12 x 12 mm) - lga option: 92-pin (7 x 7 mm) www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 2 preliminary rev. 0.8 table of contents 1. related documents and conventions . ................. ................ ................. ................ ............4 1.1. related documents........ ................ ................ ................. ................ ................. ..............4 1.1.1. sim3u1xx/sim3c1xx reference manual.................. ................. ................ ............4 1.1.2. hardware access layer (hal) api description .............. .............. .............. ..........4 1.1.3. arm cortex-m3 reference man ual................. .............. .............. .............. ............4 1.2. conventions ................ ................. ................ ................ ................. ................ .............. ...4 2. typical connection diagrams .......... .............. .............. .............. .............. .............. ............5 2.1. power ............... ................ ................ .............. .............. ............... .............. .............. .......5 3. electrical specifications............... ................ .............. .............. ............... .............. ............ ..6 3.1. electrical characteristics ......... ................ ................. .............. .............. .............. ............6 3.2. thermal conditions ........ ................ ................ ................. ................ ................. ............ 28 3.3. absolute maximum rating s.............. ................. ................ ................. ................ ..........28 4. precision32? sim3c1xx syst em overview ................ .............. .............. .............. .......... 31 4.1. power ............... ................ ................ .............. .............. ............... .............. .............. ..... 33 4.1.1. ldo and voltage regulator (v reg0) ............. .............. .............. .............. .......... 33 4.1.2. voltage supply monito r (vmon0) ............ ................ ................. ................ .......... 33 4.1.3. external regulator (extvreg 0) ................. ................. .............. .............. .......... 33 4.1.4. power management unit (pmu).......... .............. .............. .............. .............. ........ 33 4.1.5. device power modes............. ................ ................. ................ ................. ............ 34 4.2. i/o.................. ................. ................ .............. .............. .............. .............. ............. ......... 36 4.2.1. general features....... ................. ................ ................ ................. .............. ..........36 4.2.2. high drive pins (pb4) ................. ................ ................ ................. .............. ..........36 4.2.3. 5 v tolerant pins (pb3) ....... .............. .............. .............. .............. .............. .......... 36 4.2.4. crossbars .............. ................ ................ ................. ................ ................. ............ 36 4.3. clocking............ ................ ................ .............. .............. ............... .............. .............. ..... 37 4.3.1. pll (pll0)............... ................ ................. ................ ................. ................ .......... 38 4.3.2. low power oscillator (lposc 0) .............. ................ ................. ................ .......... 38 4.3.3. low frequency oscillator (lfosc 0)............... .............. .............. .............. .......... 38 4.3.4. external oscillators (extosc0 )............... ................ ................. ................ .......... 38 4.4. data peripherals.......... ................. ................ ................ ................. ................ ............... 39 4.4.1. 16-channel dma c ontroller............... .............. .............. .............. .............. .......... 39 4.4.2. 128/192/256-bit hardware aes encryption (aes0) ............... ................. ............ 39 4.4.3. 16/32-bit crc (crc0)... ................. ................. .............. .............. .............. .......... 39 4.5. counters/timers and pwm ............ ................ ................. ................ ................. ............40 4.5.1. programmable counter arra y (epca0, pca0, pca1)......... ............ ........... ........ 40 4.5.2. 32-bit timer (timer0, timer1 )............... ................ ................. ................ .......... 40 4.5.3. real-time clock (rtc0) ......... ................. ................ ................. ................ .......... 41 4.5.4. low power timer (lptimer0)... ................ ................ ................. .............. ..........41 4.5.5. watchdog timer (wdtimer0)..... ................ ................. .............. .............. ..........41 4.6. communications peripherals ....... .............. .............. .............. .............. .............. .......... 42 4.6.1. external memory interface (e mif0).......... ................ ................. ................ ..........42 4.6.2. usart (usart0, usart1)........ ................ ................. .............. .............. .......... 42 4.6.3. uart (uart0, uart1) .......... ................. ................ ................. ................ .......... 42 4.6.4. spi (spi0, spi1) ...... ................ ................. ................ ................. ................ .......... 43 www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 3 4.6.5. i2c (i2c0, i2c1)..... ................ ................ ................. ................ ................. ............ 43 4.6.6. i2s (i2s0)............... ................ ................ ................. ................ ................. ............ 44 4.7. analog .............. ................ ................ .............. .............. ............... .............. .............. ..... 45 4.7.1. 12-bit analog-to-digital converters (saradc0, saradc1). ................. ............ 45 4.7.2. sample sync generator (ssg 0) .............. ................ ................. ................ .......... 45 4.7.3. 10-bit digital-to-analog conv erter (idac0, idac1) .. ................ ................ .......... 45 4.7.4. 16-channel capacitance-to- digital converter (capsense0) . ............... ............ 46 4.7.5. low current comparators (c mp0, cmp1) ............. ................ ................. ............ 46 4.7.6. current-to-voltage c onverter (ivc0) ............ ................. .............. .............. .......... 46 4.8. reset sources............. ................. ................ ................ ................. ................ ............... 47 4.9. security ............ ................ ................ .............. .............. ............... .............. .............. ..... 48 4.10.on-chip debugging .... ................. .............. .............. .............. .............. .............. .......... 48 5. pin definitions and packag ing information............ ................ ................. .............. ..........49 5.1. sim3c1x7 pin definitions.......... ................. .............. .............. .............. .............. .......... 49 5.2. sim3c1x6 pin definitions.......... ................. .............. .............. .............. .............. .......... 57 5.3. sim3c1x4 pin definitions.......... ................. .............. .............. .............. .............. .......... 64 6. ordering information ........ ................. ................ ................ ................. ................ ............... 68 6.1. lga-92 package specificat ions.............. ................. .............. .............. .............. ..........70 6.1.1. lga-92 solder mask design ... ................. ................ ................. ................ .......... 72 6.1.2. lga-92 stencil design ........ .............. .............. .............. .............. .............. .......... 72 6.1.3. lga-92 card assembly ................ ................ ................. .............. .............. .......... 72 6.2. tqfp-80 package specifications .... ................. ................ ................. ................ .......... 73 6.2.1. tqfp-80 solder mask design. ................. ................ ................. ................ .......... 76 6.2.2. tqfp-80 stencil design ........ ................ ................. ................ ................. ............ 76 6.2.3. tqfp-80 card assembly......... ................. ................ ................. ................ .......... 76 6.3. qfn-64 package specifications .... ................ ................. ................ ................. ............ 77 6.3.1. qfn-64 solder mask design... ................. ................ ................. ................ .......... 79 6.3.2. qfn-64 stencil design ........ .............. .............. .............. .............. .............. .......... 79 6.3.3. qfn-64 card assembly ................ ................ ................. .............. .............. .......... 79 6.4. tqfp-64 package specifications .... ................. ................ ................. ................ .......... 80 6.4.1. tqfp-64 solder mask design. ................. ................ ................. ................ .......... 83 6.4.2. tqfp-64 stencil design ........ ................ ................. ................ ................. ............ 83 6.4.3. tqfp-64 card assembly......... ................. ................ ................. ................ .......... 83 6.5. qfn-40 package specifications .... ................ ................. ................ ................. ............ 84 6.5.1. qfn-40 solder mask design... ................. ................ ................. ................ .......... 86 6.5.2. qfn-40 stencil design ........ .............. .............. .............. .............. .............. .......... 86 6.5.3. qfn-40 card assembly ................ ................ ................. .............. .............. .......... 86 7. revision specific behavior............ ................. .............. .............. .............. .............. .......... 87 7.1. revision identification .... ................ ................ ................. ................ ................. ............ 87 7.2. comparator rising/falling edge flags in debug mode (cmp0, cmp1).......... ............ 88 7.2.1. problem ............ ................ ................. .............. .............. .............. .............. ..........88 7.2.2. impacts ............. ................ ................. .............. .............. .............. .............. .......... 88 7.2.3. workaround ............... ................. ................ ................ ................. .............. .......... 88 7.2.4. resolution.............. ................ ................ ................. ................ ................. ............ 88 contact information ........... ................ ................ ................. ................ ................. ............... .... 90 www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 4 preliminary rev. 0.8 1. related documents and conventions 1.1. related documents this data sheet accompanies several do cuments to provide the complete description of the sim3c1xx device family. 1.1.1. sim3u1xx/sim3c1xx reference manual the silicon laboratories sim3u1xx/sim3 c1xx reference manual pr ovides detailed functiona l descriptions for the sim3c1xx devices. 1.1.2. hardware access layer (hal) api description the silicon laboratories ha rdware access layer (hal) api provides c-language functions to modify and read each bit in the sim3c1xx devices. th is description can be found in the sim3xxxx hal api reference manual. 1.1.3. arm cortex-m3 reference manual the arm-specific features like the nested vector inte rrupt controller are described in the arm cortex-m3 reference documentation. the online reference manual can be found here: ? http://infocenter.arm.com/help/ topic/com.arm.doc.subset.cor texm.m3/index.html#cortexm3 . 1.2. conventions the block diagrams in this document use the following formatting conventions: figure 1.1. block diagram conventions internal module external memory block output_pin external to mcu block input_pin internal_output_signal internal_input_signal regn_name / bit_name dma block memory block other internal peripheral block functional block www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 5 2. typical connection diagrams this section provides typical connec tion diagrams for sim3c1xx devices. 2.1. power figure 2.1 shows a typical connection diagram for the pow er pins of the sim3c1xx devices when the internal regulator is in use. figure 2.1. connection diagram with voltage regulator used figure 2.2 shows a typical connection diagram for the pow er pins of the sim3c1xx devices when the internal regulator is not used. figure 2.2. connection diagram with voltage regulator not used sim3c1xx device vregn vregin vss vsshd 1 uf and 0.1 uf bypass capacitors required for each power pin placed as close to the pins as possible. 3.3 v (out) 5 v (in) vdd vio viohd sim3c1xx device vregn vregin vss 1.8-3.6 v (in) vsshd 1 uf and 0.1 uf bypass capacitors required for each power pin placed as close to the pins as possible. vdd vio viohd www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 6 preliminary rev. 0.8 3. electrical specifications 3.1. electrical characteristics all electrical parameters in all tables are specified unde r the conditions listed in table 3.1, unless stated otherwise. table 3.1. recommended operating conditions parameter symbol conditions min typ max units operating supply voltage on vdd v dd 1.8 ? 3.6 v operating supply voltage on vregin v regin extvreg0 not used 4 ? 5.5 v extvreg0 used 3.0 ? 3.6 v operating supply voltage on vio v io 1.8 ? v dd v operating supply voltage on viohd v iohd hv mode (default) 2.7 ? 6.0 v lv mode 1.8 ? 3.6 v voltage on i/o pins, port bank 0, 1 and 2 i/o v in v ss ? v io v voltage on i/o pins, port bank 3 i/o and reset v in sim3c1x7 pb3.0?pb3.7 and reset v ss ? v io +2.0 v sim3c1x7 pb3.8 - pb3.11 v ss ? lowest of v io +2.0 or v regin v sim3c1x6 pb3.0?pb3.5 and reset v ss ? v io +2.0 v sim3c1x6 pb3.6?pb3.9 v ss ? lowest of v io +2.0 or v regin v sim3c1x4 reset v ss ? v io +2.0 v sim3c1x4 pb3.0?pb3.3 v ss ? lowest of v io +2.0 or v regin v voltage on i/o pins, port bank 4 i/o v in v sshd ? v iohd v system clock frequency (ahb) f ahb 0 ? 80 mhz peripheral clock frequency (apb) f apb 0 ? 50 mhz operating ambient temperature t a ?40 ? 85 c operating junction temperature t j ?40 ? 105 c note: all voltages with respect to v ss . www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 7 table 3.2. power consumption parameter symbol conditions min typ max units digital core supply current normal mode 2 , 3 , 4 , 5 ?full speed with code executing from flash, peripheral clocks on i dd f ahb = 80 mhz, f apb = 40 mhz ? 33 36.5 ma f ahb = f apb = 20 mhz ? 10.5 13.3 ma f ahb = f apb = 2.5 mhz ? 2.0 3.8 ma normal mode 2 , 3 , 4 , 5 ?full speed with code executing from flash, peripheral clocks off i dd f ahb = 80 mhz, f apb = 40 mhz ? 22 24.9 ma f ahb = f apb = 20 mhz ? 7.8 10 ma f ahb = f apb = 2.5 mhz ? 1.2 3 ma power mode 1 2 , 3 , 4 , 6 ?full speed with code executing from ram, peripheral clocks on i dd f ahb = 80 mhz, f apb = 40 mhz ? 30.5 35.5 ma f ahb = f apb = 20 mhz ? 8.5 10 ma f ahb = f apb = 2.5 mhz ? 1.7 3.5 ma power mode 1 2 , 3 , 4 , 6 ?full speed with code executing from ram, peripheral clocks off i dd f ahb = 80 mhz, f apb = 40 mhz ? 20 23 ma f ahb = f apb = 20 mhz ? 5.3 7.3 ma f ahb = f apb = 2.5 mhz ? 1.0 2.8 ma power mode 2 2 , 3 , 4 ?core halted with peripheral clocks on i dd f ahb = 80 mhz, f apb = 40 mhz ? 19 22 ma f ahb = f apb = 20 mhz ? 7.8 9.7 ma f ahb = f apb = 2.5 mhz ? 1.3 3 ma power mode 3 2 , 3 i dd v dd = 1.8 v, t a = 25 c ? 175 ? a v dd = 3.0 v, t a = 25 c ? 250 ? a notes: 1. perhipheral currents drop to zero when peripheral clo ck and peripheral are disabled, unless otherwise noted. 2. currents are additive. for example, where i dd is specified and the mode is no t mutually exclusive, enabling the functions increases supply cu rrent by the specified amount. 3. i ncludes all peripherals that cannot have clocks gated in the clock control module. 4. includes supply current from internal regulato r and pll0osc (>20 mhz) or lposc0 (<=20 mhz). 5. flash execution numbers use 2 wait states for 80 mhz and 0 wait states at 20 mhz or less. 6. ram execution numbers use 0 wait states for all frequencies. 7. idac output current and ivc input current not included. 8. bias current only. does not include dynamic current from oscillator running at speed. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 8 preliminary rev. 0.8 power mode 9 2 , 3 ?low power shutdown with vreg0 disabled, powered through vdd and vio i dd rtc disabled, v dd = 1.8 v, t a = 25 c ? 85 ? na rtc w/ 16.4 khz lfo, v dd = 1.8 v, t a = 25 c ? 350 ? na rtc w/ 32.768 khz crystal, v dd = 1.8 v, t a = 25 c ? 620 ? na rtc disabled, v dd = 3.0 v, t a = 25 c ? 145 ? na rtc w/ 16.4 khz lfo, v dd = 3.0 v, t a = 25 c ? 500 ? na rtc w/ 32.768 khz crystal, v dd = 3.0 v, t a = 25 c ? 800 ? na power mode 9 2 , 3 ?low power shutdown with vreg0 in low- power mode, vdd and vio pow - ered through vreg0 (includes vreg0 current) i vregin rtc disabled, vregin = 5 v, t a = 25 c ? 300 ? na rtc w/ 16.4 khz lfo, vregin = 5 v, t a = 25 c ? 650 ? na rtc w/ 32.768 khz crystal, vregin = 5 v, t a = 25 c ? 950 ? na viohd current (high-drive i/o dis - abled) i viohd hv mode (default) ? 2.5 5 a lv mode ? 2 ? na table 3.2. power consumption (continued) parameter symbol conditions min typ max units notes: 1. perhipheral currents drop to zero when peripheral clo ck and peripheral are disabled, unless otherwise noted. 2. currents are additive. for example, where i dd is specified and the mode is no t mutually exclusive, enabling the functions increases supply cu rrent by the specified amount. 3. i ncludes all peripherals that cannot have clocks gated in the clock control module. 4. includes supply current from internal regulato r and pll0osc (>20 mhz) or lposc0 (<=20 mhz). 5. flash execution numbers use 2 wait states for 80 mhz and 0 wait states at 20 mhz or less. 6. ram execution numbers use 0 wait states for all frequencies. 7. idac output current and ivc input current not included. 8. bias current only. does not include dynamic current from oscillator running at speed. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 9 analog peripheral supply currents voltage regulator (vreg0) i vregin normal mode, t a = 25 c bgdis = 0, susen = 0 ? 300 ? a normal mode, t a = 85 c bgdis = 0, susen = 0 ? ? 650 a suspend mode, t a = 25 c bgdis = 0, susen = 1 ? 75 ? a suspend mode, t a = 85 c bgdis = 0, susen = 1 ? ? 115 a sleep mode, t a = 25 c bgdis = 1, susen = x ? 90 ? na sleep mode, t a = 85 c bgdis = 1, susen = x ? ? 500 na external regulator (extvreg0) i extvreg regulator ? 215 250 a current sensor ? 7 ? a pll0 oscillator (pll0osc) i pllosc operating at 80 mhz ? 1.75 1.86 ma low-power oscillator (lposc0) i lposc operating at 20 mhz ? 190 ? a operating at 2.5 mhz ? 40 ? a low-frequency oscillator (lfosc0) i lfosc operating at 16.4 khz, t a = 25 c ? 215 ? na operating at 16.4 khz, t a = 85 c ? ? 500 na table 3.2. power consumption (continued) parameter symbol conditions min typ max units notes: 1. perhipheral currents drop to zero when peripheral clo ck and peripheral are disabled, unless otherwise noted. 2. currents are additive. for example, where i dd is specified and the mode is no t mutually exclusive, enabling the functions increases supply cu rrent by the specified amount. 3. i ncludes all peripherals that cannot have clocks gated in the clock control module. 4. includes supply current from internal regulato r and pll0osc (>20 mhz) or lposc0 (<=20 mhz). 5. flash execution numbers use 2 wait states for 80 mhz and 0 wait states at 20 mhz or less. 6. ram execution numbers use 0 wait states for all frequencies. 7. idac output current and ivc input current not included. 8. bias current only. does not include dynamic current from oscillator running at speed. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 10 preliminary rev. 0.8 external oscillator (extosc0) 8 i extosc freqcn = 111 ? 3.8 4.7 ma freqcn = 110 ? 840 950 a freqcn = 101 ? 185 220 a freqcn = 100 ? 65 80 a freqcn = 011 ? 25 30 a freqcn = 010 ? 10 15 a freqcn = 001 ? 5 10 a freqcn = 000 ? 3 8 a saradc0, saradc1 i saradc sampling at 1 msps, highest power mode settings. ? 1.2 1.5 ma sampling at 250 ksps, lowest power mode settings. ? 390 510 a temperature sensor i tsense ? 75 105 a internal sar reference i reffs normal power mode ? 680 750 a low power mode ? 160 190 a vref0 i refp ? 75 100 a comparator 0 (cmp0), comparator 1 (cmp1) i cmp cmpmd = 11 ? 0.5 ? a cmpmd = 10 ? 3 ? a cmpmd = 01 ? 10 ? a cmpmd = 00 ? 25 ? a capacitive sensing (capsense0) i cs continuous conversions ? 55 80 a idac0 7 , idac1 7 i idac ? 75 90 a ivc0 7 i ivc i in = 0 ? 1.5 1.9 a voltage supply monitor (vmon0) i vmon ? 15 25 a table 3.2. power consumption (continued) parameter symbol conditions min typ max units notes: 1. perhipheral currents drop to zero when peripheral clo ck and peripheral are disabled, unless otherwise noted. 2. currents are additive. for example, where i dd is specified and the mode is no t mutually exclusive, enabling the functions increases supply cu rrent by the specified amount. 3. i ncludes all peripherals that cannot have clocks gated in the clock control module. 4. includes supply current from internal regulato r and pll0osc (>20 mhz) or lposc0 (<=20 mhz). 5. flash execution numbers use 2 wait states for 80 mhz and 0 wait states at 20 mhz or less. 6. ram execution numbers use 0 wait states for all frequencies. 7. idac output current and ivc input current not included. 8. bias current only. does not include dynamic current from oscillator running at speed. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 11 flash current on vdd write operation i flash-w ? ? 8 ma erase operation i flash-e ? ? 15 ma table 3.3. power mode wake up times parameter symbol conditions min typ max units power mode 3 fast wake time t pm3fw ? 425 ? s power mode 3 wake time t pm3 ? 1.35 ? ms power mode 9 wake time t pm9 ? 12 ? s table 3.2. power consumption (continued) parameter symbol conditions min typ max units notes: 1. perhipheral currents drop to zero when peripheral clo ck and peripheral are disabled, unless otherwise noted. 2. currents are additive. for example, where i dd is specified and the mode is no t mutually exclusive, enabling the functions increases supply cu rrent by the specified amount. 3. i ncludes all peripherals that cannot have clocks gated in the clock control module. 4. includes supply current from internal regulato r and pll0osc (>20 mhz) or lposc0 (<=20 mhz). 5. flash execution numbers use 2 wait states for 80 mhz and 0 wait states at 20 mhz or less. 6. ram execution numbers use 0 wait states for all frequencies. 7. idac output current and ivc input current not included. 8. bias current only. does not include dynamic current from oscillator running at speed. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 12 preliminary rev. 0.8 table 3.4. reset and supply monitor parameter symbol conditions min typ max units v dd high supply monitor threshold (vddhithen = 1) v vddmh early warning 2.10 2.20 2.30 v reset 1.95 2.05 2.1 v v dd low supply monitor threshold (vddhithen = 0) v vddml early warning 1.81 1.85 1.88 v reset 1.70 1.74 1.77 v v regin supply monitor threshold v vregm early warning 4.2 4.4 4.6 v power-on reset (por) threshold v por rising voltage on v dd ? 1.4 ? v falling voltage on v dd 0.8 1 1.3 v v dd ramp time t rmp time to v dd > 1.8 v 10 ? 3000 s reset delay from por t por relative to v dd > v por 3 ? 100 ms reset delay from non-por source t rst time between release of reset source and code execution ? 10 ? s reset low time to generate reset t rstl 50 ? ? ns missing clock detector response time (final rising edge to reset) t mcd f ahb > 1 mhz ? 0.4 1 ms missing clock detector trigger ? frequency f mcd ? 7.5 13 khz v dd supply monitor turn-on time t mon ? 2 ? s www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 13 table 3.5. on-chip regulators parameter symbol conditions min typ max units 3.3 v regulator characteristics (v reg0, supplied from vregin pin) output voltage (at vdd pin) v ddout 4 < v regin < 5.5 bgdis = 0, susen = 0 3.2 3.3 3.4 v 4 < v regin < 5.5 bgdis = 0, susen = 1 3.2 3.3 3.4 v 4 < v regin < 5.5 bgdis = 1, susen = x i ddout = 500 a 2.3 2.8 3.6 v 4 < v regin < 5.5 bgdis = 1, susen = x i ddout = 5 ma 2.1 2.65 3.3 v output current (at vdd pin)* i ddout 4 < v regin < 5.5 bgdis = 0, susen = x ? ? 150 ma 4 < v regin < 5.5 bgdis = 1, susen = x ? ? 5 ma output load regulation v ddlr bgdis = 0 ? 0.1 1 mv/ma output capacitance c vdd 1 ? 10 f *note: total current vreg0 is capable of providing. any current consumed by the sim3c1xx reduces the current available to external devices powered from vdd. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 14 preliminary rev. 0.8 table 3.6. external regulator parameter symbol conditions min typ max units input voltage range (at vre - gin) v regin 3.0 ? 3.6 v output voltage (at exregout) v exregout programmable in 100 mv steps 1.8 ? 3.6 v npn current drive i npn 400 mv dropout 12 ? ? ma pnp current drive i pnp v exregbd > v regin - 1.5 v ? 6 ? ? ma exregbd voltage (pnp mode) v exregbd v regin >= 3.5 v v regin ? 2.0 ? ? v v regin < 3.5 v 1.5 ? ? v standalone mode output current i extregbd 400mv dropout ? ? 11.5 ma external capacitance with external bjt c bjt 4.7 ? ? f standalone mode load reg - ulation lr stand - alone ? 1 ? mv/ma standalone mode external capacitance c stand - alone 47 ? ? nf current limit range i limit 1 ? sense resistor 10 ? 720 ma current limit accuracy ? ? 10 % foldback limit accuracy ? ? 20 % current sense resistor r sense ? ? 1 ? internal pull-down r pd ? 10 ? k ? internal pull-up r pu ? 5 ? k ? current sensor sensing pin voltage v extregsp v extregsn measured at extregsp or extregsn pin 2.2 ? v regin v differential sensing voltage v diff (v extregsp - v extregsn ) 10 ? 1600 mv current at extregsn pin i extregsn ? 8 ? ? a current at extregsp pin i extregsp ? v diff x 2 00 + 12 ? ? a www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 15 table 3.7. flash memory parameter symbol conditions min typ max units write time 1 t write one 16-bit half word 20 21 22 s erase time 1 t erase one page 20 21 22 ms t erall full device 20 21 22 ms v dd voltage during programming v prog 1.8 ? 3.6 v endurance (write/erase cycles) n we 20k tbd ? cycles retention 2 t ret t a = 85 c, 1k cycles tbd tbd ? years notes: 1. does not include sequencing time before and after the writ e/erase operation, which may be multiple ahb clock cycles. 2. additional data retention information is published in the quarterly quality and reliability report. table 3.8. internal oscillators parameter symbol conditions min typ max units phase-locked loop (pll0osc) calibrated output frequency* f pll0osc full temperature and supply range 77 79 80 mhz power supply sensitivity* pss pll0osc t a = 25 c, fout = 79 mhz ? 430 ? ppm/v temperature sensitivity* ts pll0osc v dd = 3.3 v, fout = 79 mhz ? 95 ? ppm/c adjustable output frequency range f pll0osc 23 ? 80 mhz lock time t pll0lock f ref = 20 mhz, f pll0osc = 80 mhz, m=24, n=99, lockth = 0 ? 1.7 ? s f ref = 32 khz, f pll0osc = 80 mhz, m=0, n=2440, lockth = 0 ? 91 ? s www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 16 preliminary rev. 0.8 low power oscillator (lposc0) oscillator frequency f lposc full temperature and supply range 19 20 21 mhz t a = 25 c, v dd = 3.3 v 19.6 20 20.4 mhz divided oscillator frequency f lposcd full temperature and supply range 2.375 2.5 2.625 mhz power supply sensitivity pss lposc t a = 25 c ? 0.5 ? %/v temperature sensitivity ts lposc v dd = 3.3 v ? 55 ? ppm/c low frequency oscillator (lfosc0) oscillator frequency f lfosc full temperature and supply range 13.4 16.4 19.7 khz t a = 25 c, v dd = 3.3 v 15.8 16.4 17.3 khz power supply sensitivity pss lfosc t a = 25 c ? 2.4 ? %/v temperature sensitivity ts lfosc v dd = 3.3 v ? 0.2 ? %/c rtc0 oscillator (rtc0osc) missing clock detector trigger frequency f rtcmcd ? 8 15 khz rtc robust duty cycle range dc rtc 25 ? 55 % *note: pll0osc in free-running oscillator mode table 3.9. external oscillator parameter symbol conditions min typ max units external input cmos clock frequency f cmos 0 ? 50 mhz external input cmos clock high time t cmosh 9 ? ? ns external input cmos clock low time t cmosl 9 ? ? ns table 3.8. internal oscillators parameter symbol conditions min typ max units www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 17 table 3.10. sar adc parameter symbol conditions min typ max units resolution n bits 12 bit mode 12 bits 10 bit mode 10 bits supply voltage requirements (vdd) v adc high speed mode 2.2 ? 3.6 v low power mode 1.8 ? 3.6 v throughput rate (high speed mode) f s 12 bit mode ? ? 250 ksps 10 bit mode ? ? 1 msps throughput rate (low power mode) f s 12 bit mode ? ? 62.5 ksps 10 bit mode ? ? 250 ksps tracking time t trk high speed mode 230 ? ? ns low power mode 450 ? ? ns sar clock frequency f sar high speed mode ? ? 16.24 mhz low power mode ? ? 4 mhz conversion time t cnv 10-bit conversion, sar clock = 16 mhz, apb clock = 40 mhz. 762.5 ns sample/hold capacitor c sar gain = 1 ? 5 ? pf gain = 0.5 ? 2.5 ? pf input pin capacitance c in high quality inputs ? 18 ? pf normal inputs ? 20 ? pf input mux impedance r mux high quality inputs ? 300 ? ? normal inputs ? 550 ? ? voltage reference range v ref 1 ? v dd v input voltage range* v in gain = 1 0 ? v ref v gain = 0.5 0 ? 2xv ref v power supply rejection ratio psrr adc ? 70 ? db dc performance integral nonlinearity inl 12 bit mode ? 1 1.9 lsb 10 bit mode ? 0.2 0.5 lsb differential nonlinearity ? (guaranteed monotonic) dnl 12 bit mode ?1 0.7 1.8 lsb 10 bit mode ? 0.2 0.5 lsb *note: absolute input pin voltage is limited by the lower of the supply at vdd and vio. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 18 preliminary rev. 0.8 offset error (using agnd) e off 12 bit mode, vref =2.4 v ?2 0 2 lsb 10 bit mode, vref =2.4 v ?1 0 1 lsb offset temperatue coefficient tc off ? 0.004 ? lsb/c slope error e m 12 bit mode ?0.07 ?0.02 0.02 % dynamic performance with external reference or internal reference in high speed mode, 10 khz sine wave input 1db below full scale, max throughput signal-to-noise snr 12 bit mode 62 66 ? db 10 bit mode 58 60 ? db signal-to-noise plus distortion sndr 12 bit mode 62 66 ? db 10 bit mode 58 60 ? db total harmonic distortion (up to 5th harmonic) thd 12 bit mode ? 78 ? db 10 bit mode ? 77 ? db spurious-free dynamic range sfdr 12 bit mode ? ?79 ? db 10 bit mode ? ?74 ? db dynamic performance with internal reference in low power mode, 10 khz sine wave input 1db below full scale, max throughput signal-to-noise snr 12 bit mode tbd 66 ? db 10 bit mode tbd 60 ? db signal-to-noise plus distortion sndr 12 bit mode tbd 66 ? db 10 bit mode tbd 60 ? db total harmonic distortion (up to 5th harmonic) thd 12 bit mode ? 78 ? db 10 bit mode ? 77 ? db spurious-free dynamic range sfdr 12 bit mode ? ?72 ? db 10 bit mode ? ?71 ? db table 3.10. sar adc (continued) parameter symbol conditions min typ max units *note: absolute input pin voltage is limited by the lower of the supply at vdd and vio. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 19 table 3.11. idac parameter symbol conditions min typ max units static performance resolution n bits 10 bits integral nonlinearity inl ? 0.5 2 lsb differential nonlinearity (guaranteed monotonic) dnl ? 0.5 1 lsb output compliance range v ocr ? ? v dd ? 1.0 v full scale output current i out 2 ma range 2.0 2.046 2.10 ma 1 ma range 1.00 1.023 1.05 ma 0.5 ma range 495 511.5 525 a offset error e off ? 250 ? na full scale error tempco tc fs 2 ma range ? 100 ? ppm/c vdd power supply rejection ratio 2 ma range ? -220 ? ppm/v test load impedance (to v ss ) r test ? 1 ? k ? dynamic performance output settling time to 1/2 lsb min output to max output ? 1.2 ? s startup time ? 3 ? s www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 20 preliminary rev. 0.8 table 3.12. capacitive sense parameter symbol conditions min typ max units single conversion time (default configuration) t single 12-bit mode ? 25 ? s 13-bit mode ? 27 ? s 14-bit mode ? 29 ? s 16-bit mode ? 33 ? s maximum external capacitive load c l highest gain setting (default) ? 45 ? pf lowest gain setting ? 500 ? pf maximum external series imped - ance c l highest gain setting (default) ? 50 ? k ? table 3.13. current-to-voltage converter (ivc) parameter symbol conditions min typ max units supply voltage (vdd) v ddivc 2.2 ? 3.6 v input pin voltage v in 2.2 ? vdd v minimum input current (source) i in 100 ? ? a integral nonlinearity inl ivc ?0.6 ? 0.6 % full scale output v ivcout ? 1.65 ? v slope m ivc input range 1 ma (inxrange = 101) 1.62 1.66 1.73 v/ma input range 2 ma (inxrange = 100) 810 830 855 mv/ma input range 3 ma (inxrange = 011) 540 550 565 mv/ma input range 4 ma (inxrange = 010) 400 415 425 mv/ma input range 5 ma (inxrange = 001) 320 330 340 mv/ma input range 6 ma (inxrange = 000) 265 275 285 mv/ma settling time to 0.1% v ivcout ? ? 500 ns www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 21 table 3.14. voltage reference electrical characteristics v dd = 1.8 to 3.6 v, ? 40 to +85 c unless otherwise specified. parameter symbol conditions min typ max units internal fast settling reference output voltage v reffs ?40 to +85 c, v dd = 1.8?3.6 v 1.62 1.65 1.68 v temperature coefficient tc reffs ? 50 ? ppm/c turn-on time t reffs ? ? 1.5 s power supply rejection psrr reffs ? 400 ? ppm/v on-chip precision reference (vref0) valid supply range v dd vref2x = 0 1.8 ? 3.6 v vref2x = 1 2.7 ? 3.6 v output voltage v refp 25 c ambient, vref2x = 0 1.195 1.2 1.205 v 25 c ambient, vref2x = 1 2.39 2.4 2.41 v short-circuit current i sc ? ? 10 ma temperature coefficient tc vrefp ? 25 ? ppm/c load regulation lr vrefp load = 0 to 200 a to vrefgnd ? 4.5 ? ppm/a load capacitor c vrefp load = 0 to 200 a to vrefgnd 0.1 ? ? f turn-on time t vrefpon 4.7 f tantalum, 0.1 f ceramic bypass ? 3.8 ? ms 0.1 f ceramic bypass ? 200 ? s power supply rejection psrr vrefp vref2x = 0 ? 320 ? ppm/v vref2x = 1 ? 560 ? ppm/v external reference input current i extref sample rate = 250 ksps; vref = 3.0 v ? 5.25 ? a www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 22 preliminary rev. 0.8 table 3.15. temperature sensor parameter symbol conditions min typ max units offset v off t a = 0 c ? 760 ? mv offset error* e off t a = 0 c ? 14 ? mv slope m ? 2.8 ? mv/c slope error* e m ? tbd ? v/c linearity ? 1 ? c turn-on time ? 1.8 ? s *note: represents one standard deviation from the mean. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 23 table 3.16. comparator parameter symbol conditions min typ max units response time, cmpmd = 00 ? (highest speed) t resp0 +100 mv differential ? 100 ? ns ?100 mv differential ? 150 ? ns response time, cmpmd = 11 ? (lowest power) t resp3 +100 mv differential ? 1.4 ? s ?100 mv differential ? 3.5 ? s positive hysterisis mode 0 (cpmd = 00) hys cp+ cmphyp = 00 ? 0.37 ? mv cmphyp = 01 ? 7.9 ? mv cmphyp = 10 ? 16.7 ? mv cmphyp = 11 ? 32.8 ? mv negative hysterisis mode 0 (cpmd = 00) hys cp- cmphyn = 00 ? 0.37 ? mv cmphyn = 01 ? ?7.9 ? mv cmphyn = 10 ? ?16.1 ? mv cmphyn = 11 ? ?32.7 ? mv positive hysterisis mode 1 (cpmd = 01) hys cp+ cmphyp = 00 ? 0.47 ? mv cmphyp = 01 ? 5.85 ? mv cmphyp = 10 ? 12 ? mv cmphyp = 11 ? 24.4 ? mv negative hysterisis mode 1 (cpmd = 01) hys cp- cmphyn = 00 ? 0.47 ? mv cmphyn = 01 ? ?6.0 ? mv cmphyn = 10 ? ?12.1 ? mv cmphyn = 11 ? ?24.6 ? mv positive hysterisis mode 2 (cpmd = 10) hys cp+ cmphyp = 00 ? 0.66 ? mv cmphyp = 01 ? 4.55 ? mv cmphyp = 10 ? 9.3 ? mv cmphyp = 11 ? 19 ? mv negative hysterisis mode 2 (cpmd = 10) hys cp- cmphyn = 00 ? 0.6 ? mv cmphyn = 01 ? ?4.5 ? mv cmphyn = 10 ? ?9.5 ? mv cmphyn = 11 ? ?19 ? mv www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 24 preliminary rev. 0.8 positive hysterisis mode 3 (cpmd = 11) hys cp+ cmphyp = 00 ? 1.37 ? mv cmphyp = 01 ? 3.8 ? mv cmphyp = 10 ? 7.8 ? mv cmphyp = 11 ? 15.6 ? mv negative hysterisis mode 3 (cpmd = 11) hys cp- cmphyn = 00 ? 1.37 ? mv cmphyn = 01 ? ?3.9 ? mv cmphyn = 10 ? ?7.9 ? mv cmphyn = 11 ? ?16 ? mv input range (cp+ or cp?) v in ?0.25 ? v dd +0.25 v input pin capacitance c cp pb2 pins ? 7.5 ? pf pb3 pins ? 10.5 ? pf common-mode rejection ratio cmrr cp ? 75 ? db power supply rejection ratio psrr cp ? 72 ? db input offset voltage v off t a = 25 c ?5 0 5 mv input offset tempco tc off ? 3.5 ? v/c reference dac resolution n bits 6 bits table 3.16. comparator (continued) parameter symbol conditions min typ max units www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 25 table 3.17. port i/o parameter symbol conditions min typ max units standard i/o (pb0, pb1, and pb2) and 5 v tolerant i/o (pb3) output high voltage v oh low drive, i oh = ?2 ma v io ? 0.7 ? ? v high drive, i oh = ?5 ma v io ? 0.7 ? ? v output low voltage v ol low drive, i ol = 3 ma ? ? 0.6 v high drive, i ol = 12.5 ma ? ? 0.6 v output rise time t r c = tbd tbd ? tbd ns output fall time t f c = tbd tbd ? tbd ns input high voltage v ih 1.8 <= v io <= 2.0 0.7 x v io ? ? v 2.0 <= v io <= 3.6 v io ? 0.6 ? ? v input low voltage v il ? ? 0.6 v pin capacitance c io pb0, pb1 and pb2 pins ? 4 ? pf pb3 pins ? 7 ? pf weak pull-up current (input voltage = 0 v) i pu v io = 1.8 ?6 ?3.5 ?2 a v io = 3.6 ?30 ?20 ?10 a input leakage ? (pullups off or analog) i lk 0 < v in < v io ?1 ? 1 a input leakage current of port bank 3 i/o, v in above v io i l v io < v in < v io +2.0 v (pins without exreg functions) 0 5 150 a v io < v in < v regin (pins with exreg functions) 0 5 150 a high drive i/o (pb4) output high voltage v oh standard mode, low drive, i oh = -3ma v iohd ? 0.7 ? ? v standard mode, high drive, i oh = -10ma v iohd ? 0.7 ? ? v output low voltage v ol standard mode, low drive, i oh = 3ma ? ? 0.6 v standard mode, high drive, i oh = 12.5ma ? ? 0.6 v output rise time t r slew rate mode 0, v iohd = 5v ? 50 ? ns slew rate mode 1, v iohd = 5v ? 300 ? ns slew rate mode 2, v iohd = 5v ? 1 ? s slew rate mode 3, v iohd = 5v ? 3 ? s www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 26 preliminary rev. 0.8 output fall time t f slew rate mode 0, v iohd = 5v ? 50 ? ns slew rate mode 1, v iohd = 5v ? 300 ? ns slew rate mode 2, v iohd = 5v ? 1 ? s slew rate mode 3, v iohd = 5v ? 3 ? s input high voltage v ih 1.8 v<= v iohd <= 2.0 v 0.7 x v iohd ? ? v 2.0 v<= v iohd <= 6 v v iohd ? 0.6 ? ? v input low voltage v il ? ? 0.6 v n-channel sink current limit (2.7 v <= v iohd <= 6 v, v ol = 0.8v) i sinkl mode 0 ? 1.76 ? ma mode 1 ? 2.34 ? mode 2 ? 3.52 ? mode 3 ? 4.69 ? mode 4 ? 7.03 ? mode 5 ? 9.38 ? mode 6 ? 14.06 ? mode 7 ? 18.75 ? mode 8 ? 28.13 ? mode 9 ? 37.5 ? mode 10 ? 56.25 ? mode 11 ? 75 ? mode 12 ? 112.5 ? mode 13 ? 150 ? mode 14 ? 225 ? mode 15 ? 300 ? total n-channel sink current on p4.0-p4.5 (dc) i sinklt ? ? 400 ma table 3.17. port i/o (continued) parameter symbol conditions min typ max units www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 27 p-channel source current limit (2.7 v <= viohd <= 6 v, v oh = viohd - 0.8v) i srcl mode 0 ? 0.88 ? ma mode 1 ? 1.17 ? mode 2 ? 1.76 ? mode 3 ? 2.34 ? mode 4 ? 3.52 ? mode 5 ? 4.69 ? mode 6 ? 7.03 ? mode 7 ? 9.38 ? mode 8 ? 14.06 ? mode 9 ? 18.75 ? mode 10 ? 28.13 ? mode 11 ? 37.5 ? mode 12 ? 56.25 ? mode 13 ? 75 ? mode 14 ? 112.5 ? mode 15 ? 150 ? total p-channel source current on p4.0-p4.5 (dc) i srclt ? ? 400 ma pin capacitance c io ? 30 ? pf weak pull-up current in low volt - age mode i pu v iohd = 1.8 v ?6 ?3.5 ?2 a v iohd = 3.6 v ?30 ?20 ?10 a weak pull-up current in high volt - age mode i pu v iohd = 2.7 v ?15 ?10 ?5 a v iohd = 6 v ?30 ?20 ?10 a input leakage (pullups off) i lk ?1 ? 1 a table 3.17. port i/o (continued) parameter symbol conditions min typ max units www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 28 preliminary rev. 0.8 3.2. thermal conditions 3.3. absolute maximum ratings stresses above those lis ted under table 3.19 may cause permanent damage to the device. this is a stress rating only and functional operation of the de vices at those or any other conditions above those indicated in the operation listings of this specification is not im plied. exposure to maximum rating condit ions for extended periods may affect device reliability. table 3.18. thermal conditions parameter symbol conditions min typ max units thermal resistance* ? ja lga-92 packages ? 35 ? c/w tqfp-80 packages ? 40 ? c/w qfn-64 packages ? 25 ? c/w tqfp-64 packages ? 30 ? c/w qfn-40 packages ? 30 ? c/w *note: thermal resistance assumes a multi-layer pcb with any exposed pad soldered to a pcb pad. table 3.19. absolute maximum ratings parameter symbol conditions min max units ambient temperature under bias t bias ?55 125 c storage temperature t stg ?65 150 c voltage on vdd v dd v ss ?0.3 4.2 v voltage on vregin v regin extvreg0 not used v ss ?0.3 6.0 v extvreg0 used v ss ?0.3 3.6 v voltage on vio v io v ss ?0.3 4.2 v voltage on viohd v iohd v ss ?0.3 6.5 v voltage on i/o pins, non port bank 3 i/ o v in reset , v io > 3.3 v v ss ?0.3 5.8 v reset , v io < 3.3 v v ss ?0.3 v io +2.5 v port bank 0, 1, and 2 i/o v ss ?0.3 v io +0.3 v port bank 4 i/o v sshd ?0.3 v iohd +0.3 v *note: vss and vsshd provide separa te return current paths for device supplies, but are not is olated. they must always be connected to the same potential on board. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 29 voltage on i/o pins, port bank 3 i/o v in sim3c1x7, pb3.0? pb3.7, v io > 3.3 v v ss ?0.3 5.8 v sim3c1x7, pb3.0? pb3.7, v io < 3.3 v v ss ?0.3 v io +2.5 v sim3c1x7, pb3.8 - pb3.11 v ss ?0.3 lowest of v io +2.5, v regin +0.3, or 5.8 v sim3c1x6, pb3.0? pb3.5, v io > 3.3 v v ss ?0.3 5.8 v sim3c1x6, pb3.0? pb3.5, v io < 3.3 v v ss ?0.3 v io +2.5 v sim3c1x6, pb3.6? pb3.9 v ss ?0.3 lowest of v io +2.5, v regin +0.3, or 5.8 v sim3c1x4, pb3.0? pb3.3 v ss ?0.3 lowest of v io +2.5, v regin +0.3, or 5.8 v total current sunk into supply pins i supp v dd , v regin , v io , v iohd ? 400 ma total current sourced out of ground pins i vss v ss, v sshd 400 ? ma current sourced or sunk by any i/o pin i pio pb0, pb1, pb2, pb3, and reset ?100 100 ma pb4 ?300 300 ma current injected on any i/o pin i inj pb0, pb1, pb2, pb3, and reset ?100 100 ma pb4 ?300 300 ma total injected current on i/o pins ? i inj sum of all i/o and reset ?400 400 ma table 3.19. absolute maximum ratings (continued) parameter symbol conditions min max units *note: vss and vsshd provide separa te return current paths for device supplies, but are not is olated. they must always be connected to the same potential on board. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 30 preliminary rev. 0.8 power dissipation at t a = 85 c p d lga-92 package ? 570 mw tqfp-80 package ? 500 mw qfn-64 package ? 800 mw tqfp-64 package ? 650 mw qfn-40 package ? 650 mw table 3.19. absolute maximum ratings (continued) parameter symbol conditions min max units *note: vss and vsshd provide separa te return current paths for device supplies, but are not is olated. they must always be connected to the same potential on board. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 31 4. precision32? sim3c1xx system overview the sim3c1xx precision32? devices are fully integrat ed, mixed-signal system-on-a-chip mcus. highlighted features are listed below. refer to table 6.1 for specif ic product feature selection and part ordering numbers. ?? core: ?? 32-bit arm cortex-m3 cpu. ?? 80 mhz maximum operating frequency. ?? branch target cache and prefetch buf fers to minimize wait states. ?? memory: 32?256 kb flash; in-system programmable, 8?32 kb sram (including 4 kb retention sram, which preserves state in pm9 mode). ?? power: ?? low drop-out (ldo) regulator for cpu core voltage. ?? power-on reset circuit and brownout detectors. ?? 3.3 v output ldo for direct power from 5 v supplies. ?? external transistor regulator. ?? power management unit (pmu). ?? i/o: up to 65 total multifunction i/o pins: ?? up to six programmable high-power capable (5?300 ma, 1.8?5 v). ?? up to twelve 5 v tolerant general purpose pins. ?? two flexible peripheral crossbars for peripheral routing. ?? clock sources: ?? internal oscillator with pll: 23 ? 80 mhz with 1.5% accuracy in free-running mode. ?? low-power internal oscillator: 20 mhz and 2.5 mhz modes. ?? low-frequency internal oscillator: 16.4 khz. ?? external rtc crystal oscillator: 32.768 khz. ?? external oscillator: crystal, rc, c, cmos clock modes. ?? programmable clock divider allows any oscillator sour ce to be divided by binary factor from 1-128. ?? data peripherals: ?? 16-channel dma controller. ?? 128/192/256-bi t hardware aes encryption. ?? 16/32-bit crc. ?? timers/counters and pwm: ?? 6-channel enhanced programmable counter array (epc an) supporting advanced pwm and capture/compare. ?? 2 x 2-channel standard programmable counter arra y (pcan) supporting pwm and capture/compare. ?? 2 x 32-bit timers - can be split into 4 x 16-b it timers, support pwm and capture/compare. ?? real time clock (rtcn). ?? low power timer. ?? watchdog timer. ?? communications peripherals: ?? external memory interface. ?? 2 x usarts and 2 x uarts with irda and iso7816 smartcard support. ?? 3 x spis. ?? 2 x i2c. ?? i 2 s (receive and transmit). ?? analog: ?? 2 x 12-bit analog-to-digital converters (saradc). ?? 2 x 10-bit digital-to-analog converter (idac). ?? 16-channel capacitance-to-digital converter (capsense). ?? 2 x low-current comparators (cmp). ?? 1 x current-to-voltage converter (ivc) module with two channels. ?? on-chip debugging with on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillator, the sim3c1xx devices are truly standalone system-on-a-chip solutions. the fl ash memory is reprogrammable in-circuit, providing non- www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 32 preliminary rev. 0.8 volatile data storage and allowing field upgrades of the firmware. user firmware ha s complete control of all peripherals and may individually shut down and gate th e clocks of any or all peripherals for power savings. the on-chip debugging interface (swj-dp) allows non-intrusive (uses no on-chi p resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, and run and halt commands. all analog and digital peripherals are fully functional while debugging. each device is specified for 1. 8 to 3.6 v operation over the industrial te mperature range (?40 to +85 c). the port i/o and reset pins are powered from the io supply voltage. the sim3c1xx devices are available in 40-pin or 64- pin qfn, 64-pin or 80-pin tqfp, or 92-pin lga packages. all package options are lead-free and rohs compliant. see table 6.1 for ordering information. a block diagram is included in figure 4.1. figure 4.1. precision32? sim3c1xx family block diagram digital usart0 usart1 uart0 uart1 i2c0 i2c1 i2s0 aes0 crc0 spi2 spi1 spi0 pca1 pca0 epca0 timer 0 timer 1 low power timer (lptimer0) voltage supply monitor (vmon0) watchdog timer (wdtimer0) arm cortex m3 core debug / programming hardware dma 16-channel controller peripheral crossbar power on reset / pmu ahb apb analog comparator 0 comparator 1 idac0 idac1 saradc0 ivc0 capacitive sensing 0 saradc1 power low dropout regulator (ldo0) voltage regulator (vreg0) external regulator (extvreg0) power management unit (pmu) memory 32/64/128/256 kb flash 4/12/28 kb ram 4 kb retention ram dma access available for these peripherals clock control clocking low frequency oscillator (lfosc0) low power oscillator (lposc0) real-time clock (rtc0osc) external oscillator control (extosc0) phase-locked loop (pll0osc) peripheral clock control (clkctrl) i/o standard i/o pins crossbars 5 v tolerant pins high drive pins emif www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 33 4.1. power 4.1.1. ldo and voltage regulator (vreg0) the sim3c1xx devices include two internal regulators : the core ldo regulator and the voltage regulator (vreg0). the ldo regulator converts a 1.8?3.6 v supply to the core operating voltage of 1.8 v. this ldo consumes little power and provides flexibility in choo sing a power supply for the system. the voltage regulator regulates from 5.5 to 2.7 v and can serve as an input to the ldo. this allows the device to be powered from up to a 5.5 v supply without any external components other than bypass capacitors. 4.1.2. voltage supply monitor (vmon0) the sim3c1xx devices include a voltage supply monitor whic h allows devices to function in known, safe operating condition without the need for external hardware. the supply monitor includes additional circuitry that can monitor the main supply voltage and the vregin input voltage divided by 4 (vregin / 4). the supply monitor module includes the following features: ?? main supply ?vdd low? (vdd below the early warning threshold) notification. ?? holds the device in reset if the main v dd supply drops below the vdd reset threshold. ?? vregin divided by 4 (vregin / 4) supply ?vregin low? notification. 4.1.3. external re gulator (extvreg0) the external regulator provides all the circuitry needed for a high-power regulator except the power transistor (npn or pnp) and current sensing resi stor (if current limiting is enabled). the external regulator module has the following features: ?? interfaces with either an npn or pnp external transistor that serves as the pass de vice for the high current regulator. ?? automatic current limiting. ?? automatic foldback limiting. ?? sources up to 1 a for use by external circuitry. ?? variable output voltage from 1.8?3.6 v in 100 mv steps. 4.1.4. power management unit (pmu) the power management unit on the sim3c1xx manages th e power systems of the device. on power-up, the pmu ensures the core voltages are a proper value before core instruction execution begins . it also recognizes and manages the various wake sources for low-power modes of the device. the pmu module includes the following features: ?? up to 16 pin wake inputs can wake the device from power mode 9. ?? the low power timer, rtc0 (alarms and oscillator fail) , comparator 0, and the reset pin can also serve as wake sources for power mode 9. ?? all pm9 wake source s (except for the reset pin) can also reset the low power timer or rtc0 modules. ?? disables the level shifters to pins and peripherals to further reduce power usage in pm9. these level shifters must be re-enabed by firmware after exiting pm9. ?? provides a pmu_asleep signal to a pin as an indicator that the device is in pm9. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 34 preliminary rev. 0.8 4.1.5. device power modes the sim3c1xx devices feature four low power modes in addition to normal operating mode. several peripherals provide wake up sources for these low power modes, in cluding the low-power timer (lpt0), rtc0 (alarms and oscillator failure notificati on), comparator 0, and pm u pin wake. all power modes are detailed in table 4.1. in addition, all peripherals can have th eir clocks disconnected to reduce po wer consumption whenever a peripheral is not being used using the cl ock control (clkctrl) registers. table 4.1. sim3c1xx power modes mode description mode entrance mode exit normal ?? core operating at full speed ?? code executing from flash power mode 1 (pm1) ?? core operating at full speed ?? code executing from ram execute code from ram jump to code in flash power mode 2 (pm2) ?? core halted ?? ahb and apb operate at full speed for peripherals wfi or wfe instructio n nvic or wic wakeup power mode 3 fast wake (pm3fw) ?? all clocks stopped except lfosc0 or rtc0osc ?? ahb and apb set to low power oscillator ?? core clock set to lfosc0 or rtc0osc ?? dmactrl0 disabled ?? fast wake mode enabled in pm3cn ?? ahb switched to low power oscillator ?? wfi or wfe instruction nvic or wic wakeup power mode 3 (pm3) all clocks stopped ?? dmactrl0 disabled ?? clocks disabled in pm3cn ?? wfi or wfe instruction nvic or wic wakeup power mode 9 (pm9) low power shutdown ?? sleepdeep set in the arm system control register ?? wfi or wfe instruction requires a reset defined by the pmu as a wake up source www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 35 4.1.5.1. normal mode normal mode encompasses the typical fu ll-speed operation. the power consumpt ion of the device in this mode will vary depending on ahb/apb clock speeds and the settings of clkctrl and the peripherals. 4.1.5.2. power mode 1 power mode 1 occurs when the core executes code from ram instead of flash. the power consumption of the device is slightly less than normal mode when in pm1. 4.1.5.3. power mode 2 in power mode 2, the core halts and the peripherals run at full speed. to place the device in this mode, the clock settings in clkctrl should remain the same as normal or power mode 1 and the core should execute a wait-for- interrupt (wfi) or wait-for-event (wfe) instruction. if the wfi instruction is ca lled from an interrup t service routine, the interrupt that wakes the device from pm2 must be of a sufficient priority to be recognized by the core. 4.1.5.4. power mode 3 fast wake power mode 3 fast wake occurs when all the clocks are stopped except for the lfosc0 or rtc0osc. the core and the peripherals are halted in this mode. the following sequence places the device in power mode 3 fast wake: 1. all dma channels must be disabled by using the global enable/disable dmaen in the dma controller (dmactrl0). 2. firmware should enable pm3 fast wake in the pm 3cn register and set the core clock to run off of the lfosc0 or rtc0osc to achieve the lowest power. 3. clkctrl control register setti ngs must be modified to set the ahb and apb clocks to the low power oscillator. 4. firmware should then execute a wfi or wfe instruction. if the wfi instruction is called from an interrupt service routine, the interrupt that wakes the device from pm3fw must be of a sufficient priority to be recognized by the core. by keeping the core clock running at a slow frequency in pm3 and changin g the ahb and apb clocks to the low power oscillator, the de vice can wake up faster than in standard power mode 3 at the expense of higher power consumption. 4.1.5.5. power mode 3 power mode 3 occurs when all the clocks are sto pped, and the core and the peripherals are halted. the following sequence places the device in power mode 3: 1. all dma channels must be disabled by using the global enable/disable dmaen in the dma controller (dmactrl0). 2. firmware should disable pm3 fast wake in the pm3cn register. 3. firmware should then execute a wfi or wfe instruction. if the wfi instruction is called from an interrupt service routine, the interrupt that wakes the devi ce from pm3 must be of a sufficient priority to be recognized by the core. 4.1.5.6. power mode 9 in power mode 9, the core and all peripherals are halted, all clocks are stopped, and the pins and peripherals are set to a lower power mode. in addition, standard ram contents are not preserved, though retention ram contents are still available after exiting the powe r mode. this mode provides the lowe st power consumption for the device, but requires an appropriate reset to exit. the available reset sources to wake from pm9 are controlled by the power management unit (pmu). to enter this mode, firmware must write the sleepdeep bit in the arm system control register. firmware must then execute a wfi or wfe instruct ion. the core will remain in pm9 unt il an enabled reset source occurs. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 36 preliminary rev. 0.8 4.2. i/o 4.2.1. general features the sim3c1xx ports have the following features: ?? push-pull or open-drain output modes and analog or digital modes. ?? option for high or low output drive strength. ?? port match allows the device to recognize a change on a port pin value. ?? internal pull-up resistors are enabled or disabled on a port-by-port basis. ?? two external interrupts with up to 16 inputs pr ovide monitoring capabilit y for external signals. ?? internal pulse generator ti mer (pb2 only) to generate simple square waves. ?? a subset of pins can also serve as inputs to the po rt mapped level shifters available on the high drive pins. 4.2.2. high drive pins (pb4) the high drive pins have the following additional features: ?? programmable safe state: high, low, or high impedance. ?? programmable drive strength and slew rates. ?? programmable current limiting. ?? powered from a separate source (viohd, which can be up to 6 v) from the rest of the device. ?? supports various functions, including gpio, uart1 pins, epca0 pins, or port mapped level shifting. 4.2.3. 5 v tolerant pins (pb3) the 5 v tolerant pins can be connected to external circui try operating at voltages above the device supply without needing extra components to shift the voltage level. 4.2.4. crossbars the sim3c1xx devices have two cro ssbars with the following features: ?? flexible peripheral assignment to port pins. ?? pins can be individually skipped to move peripherals as needed for design or layout considerations. the crossbars have a fixed priority for each i/o function an d assign these functions to t he port pins. when a digital resource is selected, the least-significant unassigned port pi n is assigned to that resource. if a port pin is assigned, the crossbars skip that pin when assi gning the next selected resource. additionally, t he crossbars will skip port pins whose associated bits in the pbskipen registers are set. this provides some flexibility when designing a system: pins involved with sensitive analog measurements can be moved away from digital i/o and peripherals can be moved around the chip as needed to ease layout constraints. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 37 4.3. clocking the sim3c1xx devices have two system clocks: ahb and apb. the ahb clock services memory peripherals and is derived from one of seven sources: the rtc0 oscillator, the low frequency oscillator, the low power oscillator, the divided low power oscillator, the exte rnal oscillator, and the pll0 oscillato r. in addition, a divider for the ahb clock provides flexible clock options for the device. the apb cloc k services data peripher als and is synchronized with the ahb clock. the apb clock can be eq ual to the ahb clock (if ahb is less t han or equal to 50 mhz) or set to the ahb clock divided by two. clock control allows the ahb and apb clo cks to be turned off to unused periph erals to save system power. any registers in a peripheral with disabled clocks will be unable to be accessed until the clocks ar e enabled. most peripherals have clocks off by default after a power-on reset. clock control apb clock ahb clock divider apb clock divider pll0 registers pbcfg and pb0/1/2/3/4 usart0 usart1 uart0 ahb clock lfosc0 lposc0 rtc0 oscillator external oscillator pll0 oscillator ram dma flash emif www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 38 preliminary rev. 0.8 4.3.1. pll (pll0) the pll module consists of a dedicate d digitally-controlled oscillator (dco) that can be used in free-running mode without a reference frequency, frequency-locked to a reference frequency, or phase-locked to a reference frequency. the reference frequency for frequency-lock and phase-lock modes can use one of multiple sources (including the external oscilla tor) to provide maximum fl exibility for different applic ation needs. because the pll module generates its own clock, the dco can be locked to a particular reference frequency and then moved to free-running mode to reduce system power and noise. the pll module includes the following features: ?? five output ranges with output frequencies ranging from 23 to 80 mhz. ?? multiple reference frequency inputs. ?? three output modes: free-running dco, frequency-locked, and phase-locked. ?? ability to sense the rising edge or falling edge of the reference source. ?? dco frequency lsb dithering to provide finer average output frequencies. ?? spectrum spreading to reduce generated system noise. ?? low jitter and fast lock times. ?? ability to suspend all output frequen cy updates (including dithering a nd spectrum spreading) using the stall bit during jitter-sensitive operations. 4.3.2. low power oscillator (lposc0) the low power oscillator is the default ahb oscilla tor on sim3c1xx devices and enables or disables automatically, as needed. the low power oscillator has the following features: ?? 20 mhz and divided 2.5 mhz frequencies available for the ahb clock. ?? automatically starts and stops as needed. 4.3.3. low frequency oscillator (lfosc0) the low frequency oscillator (lfosc0) provides a low po wer internal clock source running at approximately 16.4 khz for the rtc0 timer and other peripherals on the device. no external components are required to use the low frequency oscillator 4.3.4. external oscillators (extosc0) the extosc0 external oscillator circuit may drive an ex ternal crystal, ceramic re sonator, capacitor, or rc network. a cmos clock may also provid e a clock input. the external oscillato r output may be selected as the ahb clock or used to clock other modules independent of the ahb clock selection. the external oscillator contro l has the following features: ?? support for external crystal, rc, c, or cmos oscillators. ?? support external cmos frequencies from 10 khz to 50 mhz and external crystal frequencies from 10 khz to 30 mhz. ?? various drive strengths for flex ible crystal oscillator support. ?? internal frequency divide-by-two option available. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 39 4.4. data peripherals 4.4.1. 16-channel dma controller the dma facilitates autonomous periphe ral operation, allowing th e core to finish tasks more quickly without spending time polling or waiting for peripherals to interrup t. this helps reduce the overall power consumption of the system, as the device can spend more time in low-power modes. the dma controller has the following features: ?? utilizes arm primecell udma architecture. ?? implements 16 channels. ?? dma crossbar supports saradc0, saradc1, idac 0, idac1, i2c0, i2s0, spi0, spi1, usart0, usart1, aes0, epca0, external pin triggers, and timers. ?? supports primary, alternate, and scatter-gather data structures to implement va rious types of transfers. ?? access allowed to all ahb and apb memory space. 4.4.2. 128/192/256-bit hardware aes encryption (aes0) the basic aes block cipher is implemented in hardware. the integrated hardware support for cipher block chaining (cbc) and counter (ctr) algorithms results in identical performance, memory bandwidth, and memory footprint between the most basic electronic codebook (e cb) algorithm and these more complex algorithms. this hardware accelerator translates to more core bandwidth available for other functions or a power savings for low- power applications. the aes module includes the following features: ?? operates on 4-word (16-byte) blocks. ?? supports key sizes of 128, 192, and 256 bits for both encryption and decryption. ?? generates the round key for decryption operations. ?? all cipher operations can be performed without any firmwa re intervention for a set of 4-word blocks (up to 32 kb). ?? support for various chained and stream-ciphering configurations with xor paths on both the input and output. ?? internal 4-word fifos to facilitate dma operations. ?? integrated key storage. ?? hardware acceleration for cipher-blo ck chaining (cbc) and counter (ctr ) algorithms utiliz ing integrated counterblock generation and previous-block caching. 4.4.3. 16/32-bit crc (crc0) the crc module is designed to provide hardware calculat ions for flash memory verification and communications protocols. the crc module supports four common polynomials. the supported 32-bit polynomial is 0x04c11db7 (ieee 802.3). the three supported 16-bit polynomials are 0x 1021 (ccitt-16), 0x3d65 (iec16-mbus), and 0x8005 (zigbee, 802.15.4, and usb). the crc module includes the following features: ?? support for four common polynomials (one 32-bit and three 16-bit options). ?? byte-level bit reversal for the crc input. ?? byte-order reorientation of words for the crc input. ?? word or half-word bit reversal of the crc result. ?? ability to configure and s eed an operation in a single register write. ?? support for single-cycle paralle l (unrolled) crc computatio n for 32- or 8-bit blocks. ?? capability to crc 32 bits of da ta per peripheral bus (apb) clock. ?? support for dma writes using firmware request mode. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 40 preliminary rev. 0.8 4.5. counters/timers and pwm 4.5.1. programmable counter array (epca0, pca0, pca1) the sim3c1xx devices include two types of pca module: enhanced and standard. the enhanced programmable counter array (epca0) and standard programmable counter array (pca0, pca1) modules are timer/counter systems allowi ng for complex timing or waveform generation. multiple modules run from the same main counter, allowing for synchronous output waveforms. the enhanced pca module is multi-purpose, but is op timized for motor control applications. the epca module includes the following features: ?? three sets of channel pairs (six channels total) capable of generating complementary waveforms. ?? center- and edge-aligned waveform generation. ?? programmable dead times that ensure channel pairs are never both active at the same time. ?? programmable clock divisor and multiple options for clock source selection. ?? waveform update scheduling. ?? option to function while the core is inactive. ?? multiple synchronization triggers and outputs. ?? pulse-width modulation (pwm) waveform generation. ?? high-speed square wave generation. ?? input capture mode. ?? dma capability for both input capture and waveform generation. ?? pwm generation halt input. the standard pca module (pca) includes the following features: ?? two independent channels. ?? center- and edge-aligned waveform generation. ?? programmable clock divisor and multiple options for clock source selection. ?? pulse-width modulation waveform generation. 4.5.2. 32-bit timer (timer0, timer1) each timer module is independent, and includes the following features: ?? operation as a single 32-bit or two independent 16-bit timers. ?? clocking options include the apb cloc k, the apb clock scaled using an 8-bit prescaler, the external oscillator, or falling edges on an external input pin (synch ronized to the apb clock). ?? auto-reload functionality in both 32-bit and 16-bit modes. ?? up/down count capabilit y, controlled by an external input pin. ?? rising and falling edg e capture modes. ?? low or high pulse capture modes. ?? duty cycle capture mode. ?? square wave output mode, which is capable of toggling an external pin at a given rate with 50% duty cycle. ?? 32- or 16-bit pulse-width modulation mode. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 41 4.5.3. real-time clock (rtc0) the rtc0 module includes a 32-bit timer that allows up to 36 hours of independent time-keeping when used with a 32.768 khz watch crystal. the rtc0 provides three alarm events in addition to a missing clock event, which can also function as interrupt, reset, or wakeup sources on sim3c1xx devices. the rtc0 module includes internal loading capacitors that are programmable to 16 discrete levels, allowing compatibility with a wid e range of crystals. the rtc0 output can be buffered and routed to a port bank pin to provide an accurate, low frequency clock to other devices while the core is in its lowest power down mode. the module al so includes a low power internal low frequency oscillator that reduces low power mode current and is available for other modules to use as a clock source. the rtc module includes the following features: ?? 32-bit timer (supports up to 36 hours) with three separate alarms. ?? option for one alarm to auto matically reset the rtc timer. ?? missing clock detector. ?? can be used with the internal lo w frequency oscillator (lfosc0), an external 32.768 khz crystal (no additional resistors or capacitors nece ssary), or with an external cmos clock. ?? programmable internal loading capacitors supp ort a wide range of external 32.768 khz crystals. ?? operates directly from vdd and remains operational even when the device goes into its lowest power down mode. ?? the output can be buffered and routed to an i/o pin to provide an accurate, low frequency clock to other devices while the core is in its lowest power down mode. 4.5.4. low power timer (lptimer0) the low power timer (lptimer0) module runs from the clock selected by the rtc0 module, allowing the lptimer0 to operate even if the ahb and apb clocks are disabled. th e lptimer0 counter can increment using one of two clock sources: the clock selected by the rtc0 module, or rising or falling edges of an external signal. the low power timer includes the following features: ?? runs on a low-frequency clock (rtc0osc or lfosc0 selected in rtc0) or an external source (rising or falling edge). ?? overflow and threshold-match detection, which can gener ate an interrupt, reset the timer, or wake some devices from low power modes. ?? timer reset on threshold-match allows square-wav e generation at a variable output frequency. 4.5.5. watchdog timer (wdtimer0) the wdtimer0 module includes a 16-bit timer, a programmable early warning interrupt, and a programmable reset period. the timer registers are protected from inadvertent access by an independent lock and key interface. the watchdog timer runs from th e low frequency oscillator (lfosc0). the watchdog timer has the following features: ?? programmable timeout interval. ?? optional interrupt to warn when the watchdog timer is nearing the reset trip value. ?? lock-out feature to prevent any modification until a system reset. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 42 preliminary rev. 0.8 4.6. communicat ions peripherals 4.6.1. external memory interface (emif0) the external memory interface (emif0) allows extern al parallel asynchronous de vices, like srams and lcd controllers, to appear as part of the system memory map. the emif0 module includes the following features: ?? provides a memory mapped view of multiple external devices. ?? support for byte, half-word and word accesses regardless of external device data-width. ?? error indicator for certain invalid transfers. ?? minimum external timing allows for 3 clocks per write or 4 clocks per read. ?? output bus can be shared between non-muxed and muxed devices. ?? available extended address output allows for up to 24-bit address with 8-bit parallel devices. ?? support for 8-bit and 16-bit (muxed-mode only) devices with up to two chip-select signals. ?? support for internally muxed devices with dynamic address shifting. ?? fully programmable control signal waveforms. 4.6.2. usart (usart0, usart1) the usart uses two signals (tx and rx) and a predet ermined fixed baud rate to communicate with a single device. in addition to these signals, the usart0 module can optionally use a clock (uclk) or hardware handshaking (rts and cts). the usart module provides the following features: ?? independent transmitter and receiver configurations with separate 16-bit baud rate generators. ?? synchronous or asynchronous tr ansmissions and receptions. ?? clock master or slave operation with programmable polarity and edge controls. ?? up to 5 mbaud (synchronous or asynchronous, tx or rx, and master or slave) or 1 mbaud smartcard (tx or rx). ?? individual enables for generated clocks during start, stop, and idle states. ?? internal transmit and receive fifo s with flush capability and support fo r byte, half-word, and word reads and writes. ?? data bit lengths from 5 to 9 bits. ?? programmable inter-packet transmit delays. ?? auto-baud detection with support for the lin sync byte. ?? automatic parity generation (with enable). ?? automatic start and stop generation (with separate enables). ?? transmit and receive hardware flow-control. ?? independent inversion correction for tx, rx, rts, and cts signals. ?? irda modulation and demodulation with programmable pulse widths. ?? smartcard ack/nack support. ?? parity error, frame error, overrun, and underrun detection. ?? multi-master and half-duplex support. ?? multiple loop-back modes supported. ?? multi-processor communications support. 4.6.3. uart (u art0, uart1) the usart uses two signals (tx and rx) and a predet ermined fixed baud rate to communicate with a single device. the uart module provides the following features: ?? independent transmitter and receiver configurati ons with separate 16-bit baud-rate generators. ?? asynchronous transmissions and receptions. ?? up to 5 mbaud (tx or rx) or 1 mbaud smartcard (tx or rx). www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 43 ?? internal transmit and receive fifo s with flush capability and support fo r byte, half-word, and word reads and writes. ?? data bit lengths from 5 to 9 bits. ?? programmable inter-packet transmit delays. ?? auto-baud detection with support for the lin sync byte. ?? automatic parity generation (with enable). ?? automatic start and stop generation. ?? transmit and receive hardware flow-control. ?? independent inversion correction for tx, rx, rts, and cts signals. ?? irda modulation and demodulation with programmable pulse widths. ?? smartcard ack/nack support. ?? parity error, frame error, overrun, and underrun detection. ?? multi-master and half-duplex support. ?? multiple loop-back modes supported. 4.6.4. spi (spi0, spi1) spi is a 3- or 4-wire communication in terface that includes a clock, input da ta, output data, and an optional select signal. the spi module includes the following features: ?? supports 3- or 4-wire master or slave modes. ?? supports up to 10 mhz clock in master mode and 5 mhz clock in slave mode. ?? support for all clock phase and slave select (nss) polarity modes. ?? 16-bit programmable clock rate. ?? programmable msb-first or lsb-first shifting. ?? 8-byte fifo buffers for both transmit and receive data paths to support high speed transfers. ?? programmable fifo threshold level to request data service for dma transfers. ?? support for multiple masters on the same data lines. 4.6.5. i2c (i2c0, i2c1) the i2c interface is a two-wire, bi-directional serial bus. the two clock and data signals operate in open-drain mode with external pull-ups to su pport automatic bus arbitration. reads and writes to the interface ar e byte oriented with the i2c interfac e autonomously cont rolling the serial transfer of the data. data c an be transferred at up to 1/8th of the apb cl ock as a master or slave, which can be faster than allowed by the i2c specific ation, depending on the clock source used. a method of extending the clock- low duration is available to ac commodate devices with di fferent speed capabilit ies on the same bus. the i2c interface may operate as a master and/or slave, an d may function on a bus with multiple masters. the i2c provides control of sda (serial data), scl (serial clock) generation and synchronization, arbitration logic, and start/ stop control and generation. the i2c module includes the following features: ?? standard (up to 100 kbps) and fast (400 kbps) transfer speeds. ?? can operate down to apb clock divided by 32768 or up to apb clock divided by 8. ?? support for master, slave, and multi-master modes. ?? hardware synchronization and arbitration for multi-master mode. ?? clock low extending (clock stretching) to interface with faster masters. ?? hardware support for 7-bit slave and general call address recognition. ?? firmware support for 10-bit slave address decoding. ?? ability to disable all slave states. ?? programmable clock high and low period. ?? programmable data setup/hold times. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 44 preliminary rev. 0.8 ?? spike suppression up to 2 times the apb period. 4.6.6. i 2 s (i2s0) the i 2 s module receives digital data from an extern al source over a data line in the standard i 2 s, left-justified, right- justified, or time domain multiplexi ng format, de-serializes the data, and g enerates requests to transfer the data using the dma. the module also reads stereo audio samples from the dma, serializes the data, and sends it out of the chip on a data line in the same standard serial format for digital audio. the i 2 s receive interface consists of 3 signals: sck (bit clock), ws (word select or frame sync ), and sd (data input). the block?s transmit interface consists of 3 signals: sck (bit clock), ws (w ord select or frame sync) and sd (data output). the i 2 s module includes the following features: ?? master or slave capability. ?? flexible 10-bit clock divider with 8-bit fractional clock divider provides support for various common sampling frequencies (16 khz, 22.05 khz, 24 khz, 32 khz, 44.1 khz, and 48 khz) for up to two 32-bit channels. ?? support for dma data transfers. ?? support for various data formats. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 45 4.7. analog 4.7.1. 12-bit anal og-to-digital converters (saradc0, saradc1) the saradc0 and saradc1 modules on sim3c1xx devi ces are successive approximation register (sar) analog to digital converters (adcs). the key features of the saradc module are: ?? single-ended 12-bit and 10-bit modes. ?? supports an output update rate of 250 k samples per second in 12-bit mode or 1 m samples per second in 10-bit mode. ?? operation in low power modes at lower conversion speeds. ?? selectable asynchronous hardware conversion trigger with hardware channel select. ?? output data window comparator allows automatic range checking. ?? support for burst mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on settling and tracking time. ?? conversion complete, multiple conversion complete , and fifo overflow and underflow flags and interrupts supported. ?? flexible output data formatting. ?? sequencer allows up to 8 sources to be automatically scanned using one of four channel characteristic profiles without soft ware intervention. ?? eight-word conversion data fifo for dma operations. ?? multiple saradc modules can work together synchronously or by interleaving samples. ?? includes two internal references (1.65 v fast-settling, 1.2/2.4 v precision), support for an external reference, and support for an external signal ground. 4.7.2. sample sync generator (ssg0) the ssg module includes a phase counter and a pulse ge nerator. the phase counter is a 4-bit free-running counter clocked from the saradc module clock. counting-up from zero, the phase counter marks sixteen equally- spaced events for any number of saradc modules. the a dcs can use this phase counter to start a conversion. the programmable pulse generator creates a 50% duty cycle pulse with a period of 16 phase counter ticks. up to four programmable outputs available to external devices can be driven by the pulse generator with programmable polarity and a defined output setting when the pulse generator is stopped. the sample sync generator module has the following features: ?? connects multiple modules together to perform synchronized actions. ?? outputs a clock synchronized to th e internal sampling clock used by any number of saradc modules to pins for use by external devices. ?? includes a phase counter, pulse generator, and up to four programmable outputs. 4.7.3. 10-bit digi tal-to-analog converter (idac0, idac1) the idac takes a digital value as an input and outputs a proportional constant current on a pin. the idac module includes the following features: ?? 10-bit current dac with support for four timer, up to seven external i/o, on demand, and ssg0 output update triggers. ?? ability to update on rising, falling, or both edges for any of the ex ternal i/o trigger sources (dacntx). ?? supports an output update rate greater than 600 k samples per second. ?? support for three full-scale output mo des: 0.5 ma, 1.0 ma and 2.0 ma. ?? four-word fifo to aid with high-speed waveform generation or dma interactions. ?? individual fifo overrun, underrun, and went-empty interrupt status sources. ?? support for multiple data packing fo rmats, including: single 10-bit sample per word, dual 10-bit samples per word, or four 8-bi t samples per word. ?? support for left- and right-justified data. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 46 preliminary rev. 0.8 4.7.4. 16-channel capacitance-to -digital conver ter (capsense0) the capacitance sensing module measures capacitance on ex ternal pins and converts it to a digital value. the capsense module has th e following features: ?? multiple start-of-conversion sources (csntx). ?? option to convert to 12 , 13, 14, or 16 bits. ?? automatic threshold comparison with programmable polarit y (?less than or equal? or ?greater than?). ?? four operation modes: single conver sion, single scan, continuous single conversion, and continuous scan. ?? auto-accumulate mode that will take and average multiple samples to gether from a single start of conversion signal. ?? single bit retry options available to reduce the effect of noise during a conversion. ?? supports channel bonding to monitor multiple channe ls connected together wi th a single conversion. ?? scanning option allows the module to convert a sing le or series of channels and compare against the threshold while the ahb clock is stopped and the core is in a low power mode. 4.7.5. low current comparators (cmp0, cmp1) the comparators take two analog input voltages and output the relationship between these voltages (less than or greater than) as a digital signal. the low power comparator module includes the following features: ?? multiple sources for the positive and negative poles, including vdd, vref, and 8 i/o pins. ?? two outputs are available: a digital synchronous la tched output and a digita l asynchronous raw output. ?? programmable hysteresis and response time. ?? falling or rising edge interrupt opt ions on the co mparator output. 4.7.6. current-to-voltage converter (ivc0) the ivc module provides inputs to the saradcn modules so the input current can be measured. the ivc module has the following features: ?? two independent channels. ?? programmable input ranges (1?6 ma full-scale). www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 47 4.8. reset sources reset circuitry allows the cont roller to be easily placed in a predefined default condition. on entry to this reset state, the following occur: ?? the core halts program execution. ?? module registers are initialized to their defined reset values unless the bits reset only with a power-on reset. ?? external port pins are forced to a known state. ?? interrupts and timers are disabled. ?? clocks to all ahb peripherals are enabled. ?? clocks to all apb peripherals ot her than watchdog timer, emif 0, and dmaxbar are disabled. all registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. the contents of ram are unaffected during a reset; any previously stored data is preserved as long as power is not lost. the port i/o latches are reset to 1 in open-drain mode. weak pullups are enabled during and after the reset. for vdd supply monitor and po wer-on resets, the reset pin is driven low until the device exits the reset state. on exit from the reset state, the program counter (pc) is reset, and the system cloc k defaults to an internal oscillator. the watchdog time r is enabled with the low frequency oscilla tor (lfo0) as its clock source. program execution begins at location 0x00000000. reset sources system reset reset vdd supply monitor missing clock detector watchdog timer software reset comparator 0 comparator 1 rtc0 alarm pmu / wakeup core reset www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 48 preliminary rev. 0.8 4.9. security the peripherals on the sim3c1xx devices have a register lock and key mechanism that prevents any undesired accesses of the peripherals from firmware. each bit in th e periphlockx registers contro ls a set of peripherals. a key sequence must be written in or der to the key register to modify any of the bits in periphlockx. any subsequent write to key will then inhibit any accesses of periphlockx until it is unlocked again through key. reading the key register indicates the curr ent status of the periphlockx lock state. if a peripheral?s registers are locked, all writes will be igno red. the registers can always be read, rega rdless of the peripheral?s lock state. 4.10. on-chip debugging the sim3c1xx devices include jtag and serial wire programming and debugging interfaces and etm for instruction trace. the jtag interface is supported on si m3c1x7 and sim3c1x6 devices, and the etm interface is supported on sim3c1x7 devices. the jtag and etm inte rfaces can be optionally enabled to provide more visibility while debugging at the cost of using several port i/ o pins. additionally, if the co re is configured for serial wire (sw) mode and not jtag, then the serial wire viewer (swv) is available to provide a single pin to send out tpiu messages on sim3c1x7 and sim3c1x6 devices. most peripherals have the option to halt or contin ue functioning when the core halts in debug mode. peripheral lock and key i2c0/1 epca0, pca0/1 timer0/1 spi0/1/2 usart0/1, uart0/1 saradc0/1 ssg0 key periphlock0 periphlock1 www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 49 5. pin definitions and packaging information 5.1. sim3c1x7 pin definitions figure 5.1. sim3c1x7-gq pinout 80-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 pb4.4 pb4.5 vsshd pb4.3 pb4.2 viohd pb4.0 pb4.1 pb3.0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 pb0.11 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 vss vio pb1.13 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 nc vss vdd vio nc nc reset pb0.0 pb0.1 pb0.2 pb0.3 pb0.4 pb0.5 pb0.6 pb0.7 pb0.8 pb0.9 pb0.10 pb0.13 pb0.14 pb0.15 pb1.0 pb1.1 pb1.2/trst pb1.3/tdo/swv pb1.4/tdi pb1.5/etm0 pb1.6/etm1 vio pb1.8/etm3 pb1.9/traceclk pb1.10 pb1.11 pb1.12 pb1.14 pb2.3 pb2.4 pb2.5 pb2.6 pb2.7 pb2.8 pb2.9 pb2.10 pb2.11 pb2.12 pb2.13 pb2.14 pb3.1 pb3.2 pb3.3 pb3.4 pb3.5 pb3.6 pb3.7 pb3.8 pb3.9 pb3.10 pb3.11 swclk/tck swdio/tms pb0.12 pb1.7/etm2 pb1.15 pb2.0 pb2.1 pb2.2 vregin www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 50 preliminary rev. 0.8 figure 5.2. sim3c1x7-gm pinout vss 92 pin lga (top view) a14 d6 b9 b8 b7 b6 b5 b4 b3 b2 b1 a1 a15 b10 d5 a24 d7 b19 b20 b21 b22 b23 b24 b25 b26 b27 b28 d3 a25 a26 a27 a28 a29 a30 a31 a32 a33 a34 a16 b11 a17 b12 a18 b13 a19 b14 a20 b15 a21 b16 a22 b17 a23 b18 b36 b35 b34 b33 b32 b31 b30 b29 a47 a46 a37 d4 a45 a44 a43 a42 a41 a40 a39 a38 d1 a48 d8 a36 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 d2 a13 a35 pb0.11 vdd vio nc nc reset pb0.2 pb0.4 pb0.6 pb0.8 pb0.9 pb0.10 vregin vio pb1.13 pb1.14 pb2.3 pb2.5 pb2.7 pb2.9 pb2.11 pb2.12 pb2.13 pb2.14 pb1.15 pb2.1 pb4.4 pb4.5 pb4.3 pb4.2 viohd pb4.0 pb4.1 pb3.0 pb3.1 pb3.2 pb3.4 pb3.6 pb3.8 vsshd pb3.3 pb3.5 pb3.7 pb3.9 pb3.10 pb3.11 vss pb2.4 pb2.6 pb2.8 pb2.10 pb2.0 pb2.2 nc vss pb0.0 pb0.1 pb0.3 pb0.5 pb0.7 pb0.13 pb0.15 pb1.0 pb1.2* pb1.4* pb1.6* vio pb1.10 pb1.11 pb1.12 pb0.12 pb1.9* swdio* pb1.8* swclk* pb0.14 pb1.1 pb1.3* pb1.5* pb1.7* * noted pins are listed in the pinout table and 80-pin tqfp package figure with additional names. these alternate functions are also present on the 92-pin lga package and are identical to those on the 80-pin tqfp package. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 51 table 5.1. pin definitions and alternate functions for sim3c1x7 pin name type pin numbers tqfp-80 pin numbers lga-92 crossbar capability (see port co nfig section) port match external memory interface (m = muxed mode) port-mapped level shifter output toggle logic external trigger inputs analog or additional functions vss ground 33 75 b15 b34 vdd power (core) 74 a44 vio power (i/o) 32 49 73 a19 a29 a43 vregin power (regulator) 76 a45 vsshd ground (high drive) 4 b2 viohd power (high drive) 5 a3 reset active-low reset 80 a48 swclk / tck serial wire / jtag 45 b20 swdio / tms serial wire / jtag 44 a27 pb0.0 standard i/o 72 b33 xbr0 ? adc0.0 pb0.1 standard i/o 71 b32 xbr0 ? adc0.1 cs0.0 pb0.2 standard i/o 70 a42 xbr0 ? adc0.2 cs0.1 pb0.3 standard i/o 69 b31 xbr0 ? adc0.3 cs0.2 pb0.4 standard i/o 68 a41 xbr0 ? adc0.4 cs0.3 pb0.5 standard i/o 67 b30 xbr0 ? adc0.5 cs0.4 pb0.6 standard i/o 66 a40 xbr0 ? cs0.5 pb0.7 standard i/o 65 b29 xbr0 ? adc0.6 cs0.6 ivc0.0 www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 52 preliminary rev. 0.8 pb0.8 standard i/o 64 a39 xbr0 ? adc0.7 cs0.7 ivc0.1 pb0.9 standard i/o 63 a38 xbr0 ? adc0.8 rtc1 pb0.10 standard i/o 62 a37 xbr0 ? rtc2 pb0.11 standard i/o 61 d4 xbr0 ? adc0.9 vrefgnd pb0.12 standard i/o 60 a36 xbr0 ? adc0.10 vref pb0.13 standard i/o 59 a35 xbr0 ? idac0 pb0.14 standard i/o 58 b27 xbr0 ? idac1 pb0.15 standard i/o 57 a34 xbr0 ? xtal1 pb1.0 standard i/o 56 a33 xbr0 ? xtal2 pb1.1 standard i/o 55 b25 xbr0 ? adc0.11 pb1.2/trst standard i/o /jtag 54 a32 xbr0 ? pb1.3/tdo/ swv standard i/o /jtag/ serial wire viewer 53 b24 xbr0 ? adc0.12 adc1.12 pb1.4/tdi standard i/o /jtag 52 a31 xbr0 ? adc0.13 adc1.13 pb1.5/etm0 standard i/o /etm 51 b23 xbr0 ? adc0.14 adc1.14 pb1.6/etm1 standard i/o /etm 50 a30 xbr0 ? adc0.15 adc1.15 pb1.7/etm2 standard i/o /etm 48 b22 xbr0 ? adc1.11 cs0.8 pb1.8/etm3 standard i/o /etm 47 b21 xbr0 ? adc1.10 cs0.9 table 5.1. pin definitions and alternate functions for sim3c1x7 (continued) pin name type pin numbers tqfp-80 pin numbers lga-92 crossbar capability (see port co nfig section) port match external memory interface (m = muxed mode) port-mapped level shifter output toggle logic external trigger inputs analog or additional functions www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 53 pb1.9/ traceclk standard i/o /etm 46 a28 xbr0 ? adc1.9 pb1.10 standard i/o 43 a26 xbr0 ? a23m/ a15 dma0t1 adc1.8 pb1.11 standard i/o 42 a25 xbr0 ? a22m/ a14 dma0t0 adc1.7 pb1.12 standard i/o 41 d3 xbr0 ? a21m/ a13 adc1.6 pb1.13 standard i/o 40 a24 xbr0 ? a20m/ a12 adc0t15 wake.0 adc1.5 cs0.10 pb1.14 standard i/o 39 a23 xbr0 ? a19m/ a11 adc1t15 wake.1 adc1.4 cs0.11 pb1.15 standard i/o 38 a22 xbr0 ? a18m/ a10 wake.2 adc1.3 cs0.12 pb2.0 standard i/o 37 b17 xbr1 ? a17m/ a9 lsi0 yes int0.0 int1.0 wake.3 adc1.2 cs0.13 pb2.1 standard i/o 36 a21 xbr1 ? a16m/ a8 lsi1 yes int0.1 int1.1 wake.4 adc1.1 cs0.14 pb2.2 standard i/o 35 b16 xbr1 ? ad15m/ a7 lsi2 yes int0.2 int1.2 wake.5 adc1.0 cs0.15 pmu_asleep pb2.3 standard i/o 34 a20 xbr1 ? ad14m/ a6 lsi3 yes int0.3 int1.3 wake.6 pb2.4 standard i/o 31 b14 xbr1 ? ad13m/ a5 lsi4 yes int0.4 int1.4 wake.7 pb2.5 standard i/o 30 a18 xbr1 ? ad12m / a4 lsi5 yes int0.5 int1.5 table 5.1. pin definitions and alternate functions for sim3c1x7 (continued) pin name type pin numbers tqfp-80 pin numbers lga-92 crossbar capability (see port co nfig section) port match external memory interface (m = muxed mode) port-mapped level shifter output toggle logic external trigger inputs analog or additional functions www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 54 preliminary rev. 0.8 pb2.6 standard i/o 29 b13 xbr1 ? ad11m/ a3 yes int0.6 int1.6 pb2.7 standard i/o 28 a17 xbr1 ? ad10m/ a2 yes int0.7 int1.7 pb2.8 standard i/o 27 b12 xbr1 ? ad9m/ a1 yes pb2.9 standard i/o 26 a16 xbr1 ? ad8m/ a0 yes pb2.10 standard i/o 25 b11 xbr1 ? ad7m/ d7 yes pb2.11 standard i/o 24 a15 xbr1 ? ad6m/ d6 yes cmp0p.0 cmp1p.0 pb2.12 standard i/o 23 a14 xbr1 ? ad5m/ d5 yes cmp0n.0 cmp1n.0 rtc0osc_out pb2.13 standard i/o 22 a13 xbr1 ? ad4m/ d4 yes cmp0p.1 cmp1p.1 pb2.14 standard i/o 21 d2 xbr1 ? ad3m/ d3 yes cmp0n.1 cmp1n.1 pb3.0 5 v tolerant i/o 20 a12 xbr1 ? ad2m/ d2 cmp0p.2 cmp1p.2 pb3.1 5 v tolerant i/o 19 a11 xbr1 ? ad1m/ d1 cmp0n.2 cmp1n.2 pb3.2 5 v tolerant i/o 18 a10 xbr1 ? ad0m/ d0 dac0t0 dac1t0 lpt0t0 cmp0p.3 cmp1p.3 pb3.3 5 v tolerant i/o 17 b8 xbr1 ? wr dac0t1 dac1t1 int0.8 int1.8 cmp0n.3 cmp1n.3 table 5.1. pin definitions and alternate functions for sim3c1x7 (continued) pin name type pin numbers tqfp-80 pin numbers lga-92 crossbar capability (see port co nfig section) port match external memory interface (m = muxed mode) port-mapped level shifter output toggle logic external trigger inputs analog or additional functions www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 55 pb3.4 5 v tolerant i/o 16 a9 xbr1 ? oe int0.9 int1.9 wake.8 cmp0p.4 cmp1p.4 pb3.5 5 v tolerant i/o 15 b7 xbr1 ? alem dac0t2 dac1t2 int0.10 int1.10 wake.9 cmp0n.4 cmp1n.4 pb3.6 5 v tolerant i/o 14 a8 xbr1 ? cs0 dac0t3 dac1t3 int0.11 int1.11 wake.10 cmp0p.5 cmp1p.5 pb3.7 5 v tolerant i/o 13 b6 xbr1 ? be1 dac0t4 dac1t4 lpt0t1 int0.12 int1.12 wake.11 cmp0n.5 cmp1n.5 pb3.8 5 v tolerant i/o 12 a7 xbr1 ? cs1 dac0t5 dac1t5 lpt0t2 int0.13 int1.13 wake.12 cmp0p.6 cmp1p.6 exregsp pb3.9 5 v tolerant i/o 11 b5 xbr1 ? be0 dac0t6 dac1t6 int0.14 int1.14 wake.13 cmp0n.6 cmp1n.6 exregsn pb3.10 5 v tolerant i/o 10 b4 xbr1 ? int0.15 int1.15 wake.14 cmp0p.7 cmp1p.7 exregout pb3.11 5 v tolerant i/o 9 b3 xbr1 ? wake.15 cmp0n.7 cmp1n.7 exregbd table 5.1. pin definitions and alternate functions for sim3c1x7 (continued) pin name type pin numbers tqfp-80 pin numbers lga-92 crossbar capability (see port co nfig section) port match external memory interface (m = muxed mode) port-mapped level shifter output toggle logic external trigger inputs analog or additional functions www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 56 preliminary rev. 0.8 pb4.0 high drive i/o 8 a6 lso0 pb4.1 high drive i/o 7 a5 lso1 pb4.2 high drive i/o 6 a4 lso2 pb4.3 high drive i/o 3 a2 lso3 pb4.4 high drive i/o 2 a1 lso4 pb4.5 high drive i/o 1 d1 lso5 note: all unnamed pins on the lga-92 package ar e no-connect pins. they should be soldered to the pcb for mechanical stabil - ity, but have no internal connections to the device. table 5.1. pin definitions and alternate functions for sim3c1x7 (continued) pin name type pin numbers tqfp-80 pin numbers lga-92 crossbar capability (see port co nfig section) port match external memory interface (m = muxed mode) port-mapped level shifter output toggle logic external trigger inputs analog or additional functions www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 57 5.2. sim3c1x6 pin definitions figure 5.3. sim3c1x6-gq pinout 64 pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pb4.3 vsshd pb4.2 viohd pb4.0 pb4.1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 pb0.0 pb0.1 pb0.2 pb0.3 pb0.4 pb0.5 pb0.6 pb0.7 pb0.8 pb0.10 pb0.11 pb0.12 pb0.13 pb0.14/tdo/swv pb0.15/tdi pb1.0 pb1.1 vio pb1.3 pb1.4 pb1.5 pb3.0 pb3.1 pb3.2 pb3.3 pb3.4 pb3.5 pb3.6 pb3.7 pb3.8 pb3.9 swclk/tck swdio/tms pb0.9 pb1.2 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vss vio pb1.6 pb1.7 pb1.13 pb1.14 pb1.15 pb2.0 pb2.1 pb2.2 pb2.3 pb1.8 pb1.9 pb1.10 pb1.11 pb1.12 nc vss vdd nc nc reset vregin www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 58 preliminary rev. 0.8 figure 5.4. sim3c1x6-gm pinout vss 58 49 64 63 62 61 60 59 57 56 52 55 54 53 51 50 42 33 48 47 46 45 44 43 41 40 36 39 38 37 35 34 8 1 2 3 4 5 6 7 9 10 14 11 12 13 15 16 24 17 18 19 20 21 22 23 25 26 30 27 28 29 31 32 64 pin qfn (topview) pb0.0 pb0.1 pb0.2 pb0.3 pb0.4 pb0.5 pb0.6 pb0.7 pb0.8 nc vss vdd nc nc reset vregin pb0.10 pb0.11 pb0.12 pb0.13 pb0.14/tdo/swv pb0.15/tdi pb1.0 pb1.1 vio pb1.3 pb1.4 pb1.5 swclk/tck swdio/tms pb0.9 pb1.2 vss vio pb1.6 pb1.7 pb1.13 pb1.14 pb1.15 pb2.0 pb2.1 pb2.2 pb2.3 pb1.8 pb1.9 pb1.10 pb1.11 pb1.12 pb4.3 vsshd pb4.2 viohd pb4.0 pb4.1 pb3.0 pb3.1 pb3.2 pb3.3 pb3.4 pb3.5 pb3.6 pb3.7 pb3.8 pb3.9 www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 59 table 5.2. pin definitions and alternate functions for sim3c1x6 pin name type pin numbers crossbar capability (see port co nfig section) port match external memory interface (m = muxed mode) port-mapped level shifter output toggle logic external trigger inputs analog or additional functions vss ground 25 59 vdd power (core) 58 vio power (i/o) 24 39 vregin power (regulator) 60 vsshd ground (high drive) 2 viohd power (high drive) 3 reset active-low reset 64 swclk/tck serial wire / jtag 36 swdio/tms serial wire / jtag 35 pb0.0 standard i/o 57 xbr0 ? adc0.2 cs0.1 pb0.1 standard i/o 56 xbr0 ? adc0.3 cs0.2 pb0.2 standard i/o 55 xbr0 ? adc0.4 cs0.3 pb0.3 standard i/o 54 xbr0 ? adc0.5 cs0.4 pb0.4 standard i/o 53 xbr0 ? adc0.6 cs0.5 ivc0.0 pb0.5 standard i/o 52 xbr0 ? adc0.7 cs0.6 ivc0.1 pb0.6 standard i/o 51 xbr0 ? adc0.8 cs0.7 rtc1 www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 60 preliminary rev. 0.8 pb0.7 standard i/o 50 xbr0 ? rtc2 pb0.8 standard i/o 49 xbr0 ? adc0.9 vrefgnd pb0.9 standard i/o 48 xbr0 ? adc0.10 vref pb0.10 standard i/o 47 xbr0 ? adc1.6 idac0 pb0.11 standard i/o 46 xbr0 ? idac1 pb0.12 standard i/o 45 xbr0 ? xtal1 pb0.13 standard i/o 44 xbr0 ? xtal2 pb0.14/tdo/ swv standard i/o / jtag / serial wire viewer 43 xbr0 ? adc0.12 adc1.12 pb0.15/tdi standard i/o / jtag 42 xbr0 ? adc0.13 adc1.13 pb1.0 standard i/o 41 xbr0 ? adc0.14 adc1.14 pb1.1 standard i/o 40 xbr0 ? adc0.15 adc1.15 pb1.2 standard i/o 38 xbr0 ? adc1.11 cs0.8 pb1.3 standard i/o 37 xbr0 ? adc1.10 cs0.9 pb1.4 standard i/o 34 xbr0 ? adc1.8 pb1.5 standard i/o 33 xbr0 ? adc1.7 pb1.6 standard i/o 32 xbr0 ? adc0t15 wake.0 adc1.5 cs0.10 pb1.7 standard i/o 31 xbr0 ? ad15m/ a7 adc1t15 wake.1 adc1.4 cs0.11 table 5.2. pin definitions and alternate functions for sim3c1x6 (continued) pin name type pin numbers crossbar capability (see port co nfig section) port match external memory interface (m = muxed mode) port-mapped level shifter output toggle logic external trigger inputs analog or additional functions www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 61 pb1.8 standard i/o 30 xbr0 ? ad14m/ a6 wake.2 adc1.3 cs0.12 pb1.9 standard i/o 29 xbr0 ? ad13m/ a5 wake.3 adc1.2 cs0.13 pb1.10 standard i/o 28 xbr0 ? ad12m/ a4 dma0t1 wake.4 adc1.1 cs0.14 pb1.11 standard i/o 27 xbr0 ? ad11m/ a3 dma0t0 wake.5 adc1.0 cs0.15 pmu_asleep pb1.12 standard i/o 26 xbr0 ? ad10m/ a2 wake.6 pb1.13 standard i/o 23 xbr0 ? ad9m/ a1 pb1.14 standard i/o 22 xbr0 ? ad8m/ a0 pb1.15 standard i/o 21 xbr0 ? ad7m/ d7 pb2.0 standard i/o 20 xbr1 ? ad6m/ d6 lsi0 yes int0.0 int1.0 pb2.1 standard i/o 19 xbr1 ? ad5m/ d5 lsi1 yes int0.1 int1.1 pb2.2 standard i/o 18 xbr1 ? ad4m/ d4 lsi2 yes int0.2 int1.2 cmp0n.0 cmp1n.0 rtc0osc_out pb2.3 standard i/o 17 xbr1 ? ad3m/ d3 lsi3 yes int0.3 int1.3 cmp0p.0 cmp1p.0 pb3.0 5 v tolerant i/o 16 xbr1 ? ad2m/ d2 cmp0p.1 cmp1p.1 pb3.1 5 v tolerant i/o 15 xbr1 ? ad1m/ d1 cmp0n.1 cmp1n.1 table 5.2. pin definitions and alternate functions for sim3c1x6 (continued) pin name type pin numbers crossbar capability (see port co nfig section) port match external memory interface (m = muxed mode) port-mapped level shifter output toggle logic external trigger inputs analog or additional functions www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 62 preliminary rev. 0.8 pb3.2 5 v tolerant i/o 14 xbr1 ? ad0m/ d0 dac0t0 dac1t0 lpt0t0 wake.8 cmp0p.2 cmp1p.2 pb3.3 5 v tolerant i/o 13 xbr1 ? wr dac0t1 dac1t1 int0.4 int1.4 wake.9 cmp0n.2 cmp1n.2 pb3.4 5 v tolerant i/o 12 xbr1 ? oe int0.5 int1.5 wake.10 cmp0p.3 cmp1p.3 pb3.5 5 v tolerant i/o 11 xbr1 ? alem dac0t2 dac1t2 int0.6 int1.6 wake.11 cmp0n.3 cmp1n.3 pb3.6 5 v tolerant i/o 10 xbr1 ? cs0 dac0t3 dac1t3 int0.7 int1.7 wake.12 cmp0p.4 cmp1p.4 exregsp pb3.7 5 v tolerant i/o 9 xbr1 ? be1 dac0t4 dac1t4 int0.8 int1.8 wake.13 cmp0n.4 cmp1n.4 exregsn pb3.8 5 v tolerant i/o 8 xbr1 ? cs1 dac0t5 dac1t5 lpt0t1 int0.9 int1.9 wake.14 cmp0p.5 cmp1p.5 exregout table 5.2. pin definitions and alternate functions for sim3c1x6 (continued) pin name type pin numbers crossbar capability (see port co nfig section) port match external memory interface (m = muxed mode) port-mapped level shifter output toggle logic external trigger inputs analog or additional functions www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 63 pb3.9 5 v tolerant i/o 7 xbr1 ? be0 dac0t6 dac1t6 lpt0t2 int0.10 int1.10 wake.15 cmp0n.5 cmp1n.5 exregbd pb4.0 high drive i/o 6 lso0 pb4.1 high drive i/o 5 lso1 pb4.2 high drive i/o 4 lso2 pb4.3 high drive i/o 1 lso3 table 5.2. pin definitions and alternate functions for sim3c1x6 (continued) pin name type pin numbers crossbar capability (see port co nfig section) port match external memory interface (m = muxed mode) port-mapped level shifter output toggle logic external trigger inputs analog or additional functions www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 64 preliminary rev. 0.8 5.3. sim3c1x4 pin definitions figure 5.5. sim3c1x4-gm pinout vss 23 33 18 8 40 39 38 37 36 35 34 1 2 3 4 5 6 7 11 12 13 14 15 16 17 30 29 28 27 26 25 24 pb0.0 pb0.1 pb0.2 nc vdd nc nc reset vregin 32 31 20 19 10 9 21 22 pb0.4 pb0.5 pb0.6 pb0.8 pb0.7 pb0.9 pb0.10 swclk swdio pb0.3 40 pin qfn (top view) vss vio pb0.12 pb1.1 pb1.2 pb0.13 pb0.14 pb0.15 pb1.0 pb4.3 vsshd pb4.2 viohd pb4.0 pb4.1 pb3.0 pb3.1 pb3.2 pb3.3 pb0.11 pb1.3 www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 65 table 5.3. pin definitions and alternate functions for sim3c1x4 pin name type pin numbers crossbar capability (see port co nfig section) port match output toggle logic external trigger inputs analog or additional functions vss ground 14 vdd power (core) 35 vio power (i/o) 13 vregin power (regulator) 36 vsshd ground (high drive) 2 viohd power (high drive) 3 reset active-low reset 40 swclk serial wire 24 swdio serial wire 23 pb0.0 standard i/o 34 xbr0 ? adc0.8 cs0.7 rtc1 pb0.1 standard i/o 33 xbr0 ? rtc2 pb0.2 standard i/o 32 xbr0 ? adc0.9 cs0.0 vrefgnd pb0.3 standard i/o 31 xbr0 ? adc0.10 cs0.1 vref pb0.4 standard i/o 30 xbr0 ? adc1.6 cs0.2 idac0 pb0.5 standard i/o 29 idac1 pb0.6 standard i/o 28 xbr0 ? adc0.0 cs0.3 xtal1 pb0.7 standard i/o 27 xbr0 ? adc0.1 cs0.4 xtal2 www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 66 preliminary rev. 0.8 pb0.8 standard i/o 26 xbr0 ? adc0.14 adc1.14 pb0.9 standard i/o 25 xbr0 ? adc0.15 adc1.15 pb0.10 standard i/o 22 xbr0 ? dma0t1 adc1.8 pb0.11 standard i/o 21 xbr0 ? dma0t0 adc1.7 pb0.12 standard i/o 20 xbr0 ? adc0t15 wake.0 adc1.5 cs0.10 pb0.13 standard i/o 19 xbr0 ? adc1t15 wake.1 adc1.4 cs0.11 pb0.14 standard i/o 18 xbr0 ? wake.2 adc1.3 cs0.12 pb0.15 standard i/o 17 xbr0 ? wake.3 adc1.2 cs0.13 pb1.0 standard i/o 16 xbr0 ? wake.4 adc1.1 cs0.14 pb1.1 standard i/o 15 xbr0 ? wake.5 adc1.0 cs0.15 pmu_asleep pb1.2 standard i/o 12 xbr0 ? cmp0n.0 cmp1n.0 rtc0osc_out pb1.3 standard i/o 11 xbr0 ? cmp0p.0 cmp1p.0 pb3.0 5 v tolerant i/o 10 xbr1 ? dac0t0 dac1t0 lpt0t0 int0.0 int1.0 wake.12 cmp0p.1 cmp1p.1 exregsp table 5.3. pin definitions and alternate functions for sim3c1x4 (continued) pin name type pin numbers crossbar capability (see port config section) port match output toggle logic external trigger inputs analog or additional functions www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 67 pb3.1 5 v tolerant i/o 9 xbr1 ? dac0t1 dac1t1 lpt0t1 int0.1 int1.1 wake.13 cmp0n.1 cmp1n.1 exregsn pb3.2 5 v tolerant i/o 8 xbr1 ? dac0t2 dac1t2 lpt0t2 int0.2 int1.3 wake.14 cmp0p.2 cmp1p.2 exregout pb3.3 5 v tolerant i/o 7 xbr1 ? dac0t3 dac1t3 int0.3 int1.3 wake.15 cmp0n.2 cmp1n.2 exregbd pb4.0 high drive i/o 6 pb4.1 high drive i/o 5 pb4.2 high drive i/o 4 pb4.3 high drive i/o 1 table 5.3. pin definitions and alternate functions for sim3c1x4 (continued) pin name type pin numbers crossbar capability (see port config section) port match output toggle logic external trigger inputs analog or additional functions www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 68 preliminary rev. 0.8 6. ordering information figure 6.1. sim3c1xx part numbering all devices in the si m3c1xx family have the following features: ?? core: arm cortex-m3 with maximu m operating frequency of 80 mhz. ?? flash program memory: 32-256 kb, in-system programmable. ?? ram: 8?32 kb sram, with 4 kb retention sram ?? i/o: up to 65 multifunction i/o pins, including high-drive and 5 v-tolerant pins. ?? clock sources: internal and external oscillator options. ?? 16-channel dma controller. ?? 128/192/256-bit aes. ?? 16/32-bit crc. ?? timers: 2 x 32-bit (4 x 16-bit). ?? real-time clock. ?? low-power timer. ?? pca: 1 x 6 channels (enhanced), 2 x 2 channels (sta ndard). pwm, capture, and clock generation capabilites. ?? adc: 2 x 12-bit 250 ksps (10-bit 1 msps) sar. ?? dac: 2 x 10-bit idac. ?? temperature sensor. ?? internal vref. ?? 16-channel capacitive sensing (capsense). ?? comparator: 2 x low current. ?? current to voltage converter (ivc). ?? serial buses: 2 x usart, 2 x uart, 3 x spi, 2 x i2c, 1 x i 2 s. the inclusion of some features varies across different memb ers of the device family. the differences are detailed in table 6.1. si m3 c 1 4 4 ? b gm ? silicon labs core ? m3 (cortex m3) family ? u (usb), c (core) feature set ? varies by family memory size ? 3 (32 kb), 4 (64 kb), 5 (128 kb), 6 (256 kb) pin count ? 4 (40 pin), 6 (64 pin), 7 (80 or 92 pin) revision temperature grade and package type www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 69 table 6.1. product selection guide ordering part number flash memory (kb) ram (kb) external memory interface (emif) maximum number of emif address/data pins digital port i/os (total) digital port i/os with high drive capability number of saradc0 channels number of saradc1 channels number of capsense0 channels number of comparator 0/1 inputs (+/-) number of pmu pin wake sources jtag debugging interface etm debugging interface serial wire debugging interface lead-free (rohs compliant) package sim3c167-b-gm 256 32 ? 2465 6 1616168/816 ???? lga-92 sim3c167-b-gq 256 32 ? 2465 6 1616168/816 ???? tqfp-80 sim3c166-b-gm 256 32 ? 1650 4 1315156/615 ? ?? qfn-64 sim3c166-b-gq 256 32 ? 1650 4 1315156/615 ? ?? tqfp-64 sim3c164-b-gm 256 32 28 4 7 11 12 3/3 10 ?? qfn-40 sim3c157-b-gm 128 32 ? 2465 6 1616168/816 ???? lga-92 sim3c157-b-gq 128 32 ? 2465 6 1616168/816 ???? tqfp-80 sim3c156-b-gm 128 32 ? 1650 4 1315156/615 ? ?? qfn-64 sim3c156-b-gq 128 32 ? 1650 4 1315156/615 ? ?? tqfp-64 sim3c154-b-gm 128 32 28 4 7 11 12 3/3 10 ?? qfn-40 sim3c146-b-gm 64 16 ? 1650 4 1315156/615 ? ?? qfn-64 sim3c146-b-gq 64 16 ? 1650 4 1315156/615 ? ?? tqfp-64 sim3c144-b-gm 64 16 28 4 7 11 12 3/3 10 ?? qfn-40 sim3c136-b-gm 32 8 ? 1650 4 1315156/615 ? ?? qfn-64 SIM3C136-B-GQ 32 8 ? 1650 4 1315156/615 ? ?? tqfp-64 sim3c134-b-gm 32 8 28 4 7 11 12 3/3 10 ?? qfn-40 www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 70 preliminary rev. 0.8 6.1. lga-92 pack age specifications figure 6.2. lga-92 package drawing table 6.2. lga-92 package dimensions dimension min nominal max a 0.74 0.84 0.94 b 0.25 0.30 0.35 c 3.15 3.20 3.25 d 7.00 bsc d1 6.50 bsc d2 4.00 bsc e 0.50 bsc e 7.00 bsc e1 6.50 bsc e2 4.00 bsc aaa ? ? 0.10 bbb ? ? 0.10 ccc ? ? 0.08 ddd ? ? 0.10 eee ? ? 0.10 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 71 figure 6.3. lga-92 landing diagram table 6.3. lga-92 landing diagram dimensions dimension typical max c1 6.50 ? c2 6.50 ? e 0.50 ? f ? 0.35 p1 ? 3.20 p2 ? 3.20 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. 3. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 4. this land pattern design is based on the ipc-7351 guidelines. ? www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 72 preliminary rev. 0.8 6.1.1. lga-92 solder mask design all metal pads are to be non-solder mask defined (nsmd) . clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. 6.1.2. lga-92 stencil design 1. a stainless steel, laser-cut and electro-polished sten cil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 4. a 2 x 2 array of 1.25 mm square openings on 1. 60 mm pitch should be used for the center ground pad. 6.1.3. lga-92 card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per t he jedec/ipc j-std-020 specification for small body components. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 73 6.2. tqfp-80 pa ckage specifications figure 6.4. tqfp-80 package drawing table 6.4. tqfp-80 package dimensions dimension min nominal max a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 b 0.17 0.20 0.27 c 0.09 ? 0.20 d 14.00 bsc d1 12.00 bsc e 0.50 bsc e 14.00 bsc e1 12.00 bsc www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 74 preliminary rev. 0.8 l 0.45 0.60 0.75 l1 1.00 ref ? 0 3.5 7 aaa 0.20 bbb 0.20 ccc 0.08 ddd 0.08 eee 0.05 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this package outline conforms to jedec ms-026, variant add. 4. recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components. table 6.4. tqfp-80 package dimensions (continued) dimension min nominal max www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 75 figure 6.5. tqfp-80 landing diagram table 6.5. tqfp-80 landing diagram dimensions dimension min max c1 13.30 13.40 c2 13.30 13.40 e 0.50 bsc x 0.20 0.30 y 1.40 1.50 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. ? www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 76 preliminary rev. 0.8 6.2.1. tqfp-80 solder mask design all metal pads are to be non-solder mask defined (nsmd) . clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. 6.2.2. tqfp-80 stencil design 1. a stainless steel, laser-cut and electro-polished sten cil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all pads. 6.2.3. tqfp-80 card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per t he jedec/ipc j-std-020 specification for small body components. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 77 6.3. qfn-64 package specifications figure 6.6. qfn-64 package drawing table 6.6. qfn-64 package dimensions dimension min nominal max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 9.00 bsc d2 3.95 4.10 4.25 e 0.50 bsc e 9.00 bsc e2 3.95 4.10 4.25 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this package outline conforms to jedec mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 78 preliminary rev. 0.8 figure 6.7. qfn-64 landing diagram table 6.7. qfn-64 landing diagram dimensions dimension mm c1 8.90 c2 8.90 e 0.50 x1 0.30 y1 0.85 x2 4.25 y2 4.25 notes: 1. all dimensions shown are in millimeters (mm). 2. this land pattern design is based on the ipc-7351 guidelines. 3. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. ? www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 79 6.3.1. qfn-64 solder mask design all metal pads are to be non-solder mask defined (nsmd) . clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. 6.3.2. qfn-64 stencil design 1. a stainless steel, laser-cut and electro-polished sten cil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all pads. 4. a 3x3 array of 1.0 mm square openings on a 1. 5 mm pitch should be used for the center ground pad. 6.3.3. qfn-64 card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per t he jedec/ipc j-std-020 specification for small body components. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 80 preliminary rev. 0.8 6.4. tqfp-64 pa ckage specifications figure 6.8. tqfp-64 package drawing table 6.8. tqfp-64 package dimensions dimension min nominal max a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 ? 0.20 d 12.00 bsc d1 10.00 bsc e 0.50 bsc e 12.00 bsc e1 10.00 bsc l 0.45 0.60 0.75 ? 0 3.5 7 www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 81 aaa ? ? 0.20 bbb ? ? 0.20 ccc ? ? 0.08 ddd ? ? 0.08 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this package outline conforms to jedec ms-026, variant acd. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. table 6.8. tqfp-64 package dimensions (continued) dimension min nominal max www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 82 preliminary rev. 0.8 figure 6.9. tqfp-64 landing diagram table 6.9. tqfp-64 landing diagram dimensions dimension min max c1 11.30 11.40 c2 11.30 11.40 e 0.50 bsc x 0.20 0.30 y 1.40 1.50 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. ? www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 83 6.4.1. tqfp-64 solder mask design all metal pads are to be non-solder mask defined (nsmd) . clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. 6.4.2. tqfp-64 stencil design 1. a stainless steel, laser-cut and electro-polished sten cil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all pads. 6.4.3. tqfp-64 card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per t he jedec/ipc j-std-020 specification for small body components. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 84 preliminary rev. 0.8 6.5. qfn-40 package specifications figure 6.10. qfn-40 package drawing table 6.10. qfn-40 package dimensions dimension min nominal max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 6.00 bsc d2 4.35 4.50 4.65 e 0.50 bsc e 6.00 bsc e2 4.35 4.5 4.65 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this package outline conforms to jedec mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 85 figure 6.11. qfn-40 landing diagram table 6.11. qfn-40 landing diagram dimensions dimension mm c1 5.90 c2 5.90 e 0.50 x1 0.30 y1 0.85 x2 4.65 y2 4.65 notes: 1. all dimensions shown are in millimeters (mm). 2. this land pattern design is based on the ipc-7351 guidelines. 3. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 86 preliminary rev. 0.8 6.5.1. qfn-40 solder mask design all metal pads are to be non-solder mask defined (nsmd) . clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. 6.5.2. qfn-40 stencil design 1. a stainless steel, laser-cut and electro-polished sten cil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all pads. 4. a 3x3 array of 1.1 mm square openings on a 1. 6 mm pitch should be used for the center ground pad. 6.5.3. qfn-40 card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per t he jedec/ipc j-std-020 specification for small body components. www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 87 7. revision specific behavior this chapter details any known differences from behavior as stated in the device datasheet and reference manual. all known errata for the current silicon re vision are rolled into this section at the time of publication. any errata found after publication of this document will initially be detailed in a separa te errata document unt il this datasheet is revised. 7.1. revision identification the lot id code on the top side of the device package can be used for decoding device revision information. figures 7.1, 7.2, 7.3, and 7.4 show how to find the lot id code on the top side of the device package. in addition, firmware can determine the revision of the device by checking the deviceid registers. figure 7.1. lga-92 sim3c1x7 revision information figure 7.2. tqfp-80 sim3c1x7 revision information sim3c167 b gnzeb 1142 this first character identifies the device revision this character identifies the device revision sim3c167 a-gq 1131 b cs701 tw e3 www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 88 preliminary rev. 0.8 figure 7.3. sim3c1x6 revision information figure 7.4. sim3c1x4 revision information 7.2. comparator rising/ falling edge flags in de bug mode (cmp0, cmp1) 7.2.1. problem on revision a and revision b devices, if the comparator output is high, the comparator risi ng and falling edge flags will both be set to 1 upon single-step or exit from debug mode. 7.2.2. impacts firmware using the rising and falling edge flags to make de cisions may see a false trigge r of the comparator if the output of the comparator is high during a debug session. this does not impact the non-debug operation of the device. 7.2.3. workaround there is not a system-agnostic workaround for this issue. 7.2.4. resolution this issue exists on revision a and revision b devi ces. it may be corrected in a future device revision. sim3c166 b gnzeb 1142 this first character identifies the device revision sim3c166 b gnzeb 1142 sil m3c164 b gnz 1142+ this first character identifies the device revision www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx preliminary rev. 0.8 89 n otes : www.datasheet.co.kr datasheet pdf - http://www..net/
sim3c1xx 90 preliminary rev. 0.8 c ontact i nformation silicon laboratories inc. 400 west cesar chavez ? austin, tx 78701 please visit the silicon labs technical support web page: ? https://www.silabs.com/support/pages/contacttechnicalsupport.aspx ? and register to submit a technical support request. silicon laboratories, silicon labs, and precisi on32 are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders the information in this document is believed to be accurate in a ll respects at the time of public ation but is subject to change without notice. silicon laboratories assumes no responsibi lity for errors and omissions , and disclaims responsibilit y for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratories assumes no responsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warranty, representation or guarantee regarding the suitability of its produ cts for any particular purpose, nor does silicon laboratories assume any liability arising out of the application or use of any product or ci rcuit, and specifically discla ims any and all liability, in cluding without limitation consequential or incidental damages . silicon laboratories products are not designed, intended, or authorized for use in applica tions intended to support or sustain life, or for any other application in wh ich the failure of the silicon laboratories product could create a situation where personal injury or death may occur. shoul d buyer purchase or use silicon laborator ies products for any such unintended or unaut horized application, buyer shall indemnify and hold silic on laboratories harmless against all claims and damages. www.datasheet.co.kr datasheet pdf - http://www..net/

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